CP80C88Z Ver la hoja de datos (PDF) - Intersil

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CP80C88Z

CMOS 8-/16-Bit Microprocessor

Intersil 

Waveforms (Continued)

80C88

CLK (82C84A OUTPUT)

AD7-AD0

WRITE CYCLE

DEN

WR

AD7-AD0

INTA CYCLE

(NOTE 11)

RD, WR = VOH

DT/R

INTA

DEN

T1

T2

(4)

TCH1CH2

(17)

TCLAV

(26)

TCLDV

TCLAX

(18)

AD7-AD0

TCVCTV (29)

(29) TCVCTV

(19)

TCLAZ

TCHCTV

(30)

(29) TCVCTV

(29) TCVCTV

T3 TW

T4

(5)

TCL2CL1

TW

(27)

TCLDX2

DATA OUT

(31) TCVCTX

TWHDX

(28)

(38)

TWLWH

TCVCTX (31)

TDVCL (6)

POINTER

TCLDX1 (7)

TCHCTV (30)

TCVCTX

(31)

SOFTWARE

HALT -

DEN, RD,

WR, INTA = VOH

AD7-AD0

ALE

IO/M

DT/R

SSO

TCLAV

(17)

TCHCTV

(30)

INVALID ADDRESS

SOFTWARE HALT

TCHLL

(24)

TCLLH

(23)

TCVCTX

(31)

NOTES:

FIGURE 10. BUS TIMING - MINIMUM MODE SYSTEM (Continued)

1. Two INTA cycles run back-to-back. The 80C88 local ADDR/DATA bus is floating during both INTA cycles. Control signals are shown for the

second INTA cycle.

2. Signals at 82C84A are shown for reference only.

20

FN2949.4

February 22, 2008

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