LC99062-W50 Ver la hoja de datos (PDF) - SANYO -> Panasonic

Número de pieza

componentes Descripción

Fabricante

LC99062-W50

Image Sensor Signal Processing LSI

SANYO -> Panasonic 

Pin Functions

Pin No.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

Symbol

TV

MIRROR

VDD

VSS

FSC4

VD62

HD62

APTSW

HTCLK

TESDATA

CDSIN0

CDSIN1

CDSIN2

CDSIN3

CDSIN4

CDSIN5

CDSIN6

CDSIN7

VDD

VSS

OT1

OT2

OT3

OT4

OT5

OT6

OT7

OT8

OT24

OT23

OT22

OT21

OT20

OT19

OT18

OT17

OT16

OT15

OT14

VSS

VDD

OT13

OT12

OT11

OT10

OT9

REGSEL0

REGSEL1

REGSEL2

REGSEL3

REGSEL4

CSSET1

SUPER

CKEYH

LC99062-W50

I/O → I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: Unconnected pin

I/O

Function

I 0: NTSC, 1: PAL

I 0: Normal, 1: Mirror

P

P

I CLK (from LC99052) NTSC: 14.31818 MHz, PAL: 14.1875 MHz

I VD (from LC99052)

I HD (from LC99052)

I Aperture switch 0: Off, 1: On

I CLK = 8/3fsc (from LC99052)

I 0: Run

I 8-bit data input (from LC99052) (LSB)

I 8-bit data input (from LC99052)

I 8-bit data input (from LC99052)

I 8-bit data input (from LC99052)

I 8-bit data input (from LC99052)

I 8-bit data input (from LC99052)

I 8-bit data input (from LC99052)

I 8-bit data input (from LC99052) (MSB)

P

P

O Output channel1 = CH1 (LSB)

O Output channel1 = CH1

O Output channel1 = CH1

O Output channel1 = CH1

O Output channel1 = CH1

O Output channel1 = CH1

O Output channel1 = CH1

O Output channel1 = CH1 (MSB)

O Output channel3 = CH3 (MSB)

O Output channel3 = CH3

O Output channel3 = CH3

O Output channel3 = CH3

O Output channel3 = CH3

O Output channel3 = CH3

O Output channel3 = CH3

O Output channel3 = CH3 (LSB)

O Output channel2 = CH2 (MSB)

O Output channel2 = CH2

O Output channel2 = CH2

P

P

O Output channel2 = CH2

O Output channel2 = CH2

O Output channel2 = CH2

O Output channel2 = CH2

O Output channel2 = CH2 (LSB)

I (REGRES) 0: Register initialization 1: Register modification allowed

I (CLKS) Serial clock input

I (DATAS) Serial data input

I

I REGSEL [4:0] = (11110) or (11**1); OT (24 to 1) → High impedance

Must be set according to the phase of the LC99052 A/D converter clock. (This is true for pin 81 as well.)

I

Recommended value for current conditions: 1

I Superimpose pulse input 1; superimpose 0; camera through

Chrominance key out H; chrominance key

O The delay time is changed by the settings of pins 85 and 86. See pins 85 and 86.

Continued on next page.

No. 5073-3/7

Share Link: