M4A5-32/32-7VI Ver la hoja de datos (PDF) - Lattice Semiconductor
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M4A5-32/32-7VI Datasheet PDF : 63 Pages
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ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1
-5
-55
-6
-65
-7
-10
-12
-14
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
Combinatorial Delay:
tPDi
Internal combinatorial propagation
delay
3.5
4.0
4.3
4.5
5.0
7.0
9.0
11.0 ns
tPD Combinatorial propagation delay
Registered Delays:
5.0
5.5
6.0
6.5
7.5
10.0
12.0
14.0 ns
tSS
Synchronous clock setup time, D-type
register
3.0
3.5
3.5
3.5
5.0
5.5
7.0
10.0
ns
tSST
Synchronous clock setup time, T-type
register
4.0
4.0
4.0
4.0
6.0
6.5
8.0
11.0
ns
Asynchronous clock setup time, D-type
tSA register
2.5
2.5
2.5
3.0
3.5
4.0
5.0
8.0
ns
tSAT
Asynchronous clock setup time, T-type
register
3.0
3.0
3.0
3.5
4.5
5.0
6.0
9.0
ns
tHS Synchronous clock hold time
tHA Asynchronous clock hold time
tCOSi Synchronous clock to internal output
tCOS Synchronous clock to output
tCOAi Asynchronous clock to internal output
tCOA Asynchronous clock to output
Latched Delays:
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
2.5
2.5
2.5
3.0
3.5
4.0
5.0
8.0
ns
2.5
2.5
2.8
3.0
3.0
3.0
3.5
3.5 ns
4.0
4.0
4.5
5.0
5.5
6.0
6.5
6.5 ns
5.0
5.0
5.0
5.0
6.0
8.0
10.0
12.0 ns
6.5
6.5
6.8
7.0
8.5
11.0
13.0
15.0 ns
tSSL Synchronous latch setup time
tSAL Asynchronous latch setup time
tHSL Synchronous latch hold time
tHAL Asynchronous latch hold time
tPDLi Transparent latch to internal output
tPDL
Propagation delay through transparent
latch to output
4.0
4.0
4.0
4.5
6.0
7.0
8.0
10.0
ns
3.0
3.0
3.5
3.5
4.0
4.0
5.0
8.0
ns
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
3.0
3.0
3.5
3.5
4.0
4.0
5.0
8.0
ns
5.5
5.5
5.8
6.0
7.5
9.0
11.0
12.0 ns
7.0
7.0
7.5
8.0
10.0
12.0
14.0
15.0 ns
tGOSi Synchronous gate to internal output
tGOS Synchronous gate to output
tGOAi Asynchronous gate to internal output
tGOA Asynchronous gate to output
Input Register Delays:
3.0
3.0
3.0
3.0
3.5
4.5
7.0
8.0 ns
4.5
4.5
4.8
5.0
6.0
7.5
10.0
11.0 ns
6.0
6.0
6.0
6.0
8.5
10.0
13.0
15.0 ns
7.5
7.5
7.8
8.0
11.0
13.0
16.0
18.0 ns
tSIRS Input register setup time
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
ns
tHIRS Input register hold time
2.5
2.5
3.0
3.0
3.0
3.0
3.0
4.0
ns
tICOSi Input register clock to internal feedback
3.0
3.0
3.0
3.0
3.5
4.5
6.0
6.0 ns
Input Latch Delays:
tSIL Input latch setup time
tHIL Input latch hold time
tIGOSi Input latch gate to internal feedback
tPDILi
Transparent input latch to internal
feedback
1.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
ns
2.5
2.5
2.5
3.0
3.0
3.0
3.0
4.0
ns
3.5
3.5
3.8
4.0
4.0
4.0
4.0
5.0 ns
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0 ns
38
ispMACH 4A Family
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