AS7C1024-20(2001_03) Ver la hoja de datos (PDF) - Alliance Semiconductor

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Fabricante

AS7C1024-20
(Rev.:2001_03)

5V/3.3V 128K×8 CMOS SRAM (Evolutionary Pinout)

Alliance Semiconductor 

®

Write cycle (over the operating range)11, 12

Parameter

Write cycle time

Chip enable (CE1) to write end

Chip enable (CE2) to write end

Address setup to write end

Address setup time

Write pulse width

Address hold from end of write

Data valid to write end

Data hold time

Write enable to output in high Z

Output active from write end

Shaded areas contain advance information.

Symbol

tWC

tCW1

tCW2

tAW

tAS

tWP

tAH

tDW

tDH

tWZ

tOW

-12

Min Max

12 –

10 –

10 –

10 –

0

–

8

–

0

–

6

–

0

–

–

5

3

–

-15

Min Max

15 –

12 –

12 –

12 –

0

–

9

–

0

–

9

–

0

–

–

5

3

–

-20

Min Max

20

–

12

–

12

–

12

–

0

–

12

–

0

–

10

–

0

–

–

5

3

–

Write waveform 1 ( WE controlled)10,11,12

tWC

tAW

Address

tWP

WE

tAS

DIN

tWZ

DOUT

tAH

tDW

tDH

Data valid

tOW

AS7C1024

AS7C31024

Unit Notes

ns

ns

12

ns

12

ns

ns

12

ns

ns

ns

ns

4, 5

ns

4, 5

ns

4, 5

Write waveform 2 (CE1 and CE2 controlled)10,11,12

tWC

tAW

Address

tAS

tCW1, tCW2

CE1

CE2

tWP

WE

tWZ

tDW

DIN

Data valid

DOUT

tAH

tDH

3/23/01; v.1.0

Alliance Semiconductor

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