DCLK
LOAD
OUT ( H--> L)
OUT ( L--> H)
HM10S604 PRELIMINARY SPEC
Tw3 > 63 DCLK cycle
High - Z
thiz
Fig 5. Timing Waveform
td2
td3
LOAD
POLC
Odd Outputs
High-Z GL63 ~GL0 High-Z GH63 ~GH0 High-Z GL63 ~GL0 High-Z GH63 ~GH0
Even Outputs
High-Z GH63 ~GH0 High-Z GL63 ~GL0 High-Z GH63 ~GH0 High-Z GL63 ~GL0
Fig 6. Relationship between LOAD, POLC, and outputs
• CONFIDENTIAL & PROPRIETARY