AD7829-1 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
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AD7829-1 Datasheet PDF : 20 Pages
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AD7829-1
TIMING CHARACTERISTICS
VREF IN/OUT = 2.5 V. All specifications −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter1, 2
t1
t2
t3
t4
t5
t6
t7
t8
t93
t104
t11
t12
t13
tPOWER UP
tPOWER UP
5 V ± 10%
420
20
30
110
70
10
0
0
30
10
5
20
10
15
200
25
1
3 V ± 10%
420
20
30
110
70
10
0
0
30
20
5
20
10
15
200
25
1
Unit
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
μs typ
μs max
Description
Conversion time
Minimum CONVST pulse width
Minimum time between the rising edge of RD and the next falling edge of convert start
EOC pulse width
RD rising edge to EOC pulse high
CS to RD setup time
CS to RD hold time
Minimum RD pulse width
Data access time after RD low
Bus relinquish time after RD high
Address setup time before the falling edge of RD
Address hold time after the falling edge of RD
Minimum time between new channel selection and convert start
Power-up time from the rising edge of CONVST using on-chip reference
Power-up time from the rising edge of CONVST using external 2.5 V reference
1 Sample tested to ensure compliance.
2 See Figure 21, Figure 22, and Figure 23.
3 Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V with VDD = 5 V ± 10%, and the time required for an
output to cross 0.4 V or 2.0 V with VDD = 3 V ± 10%.
4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish time
of the part and, as such, is independent of external bus loading capacitances.
TIMING DIAGRAM
200µA
IOL
TO OUTPUT
PIN CL
50pF
2.1V
200µA
IOH
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
Rev. 0 | Page 5 of 20
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