M50LPW012
Table 15. Low Pin Count Register Configuration Map(1)
Mnemonic
Register Name
Memory Address
Top
Bottom
T_BLOCK_LK Top Block Lock Register (Block 6)
FF7FC002h 008FC002h
T_MINUS01_LK Top Block [-1] Lock Register (Block 5) FF7FA002h 008FA002h
T_MINUS02_LK Top Block [-2] Lock Register (Block 4) FF7F8002h
008F8002h
T_MINUS03_LK Top Block [-3] Lock Register (Block 3) FF7F0002h
008F0002h
T_MINUS04_LK Top Block [-4] Lock Register (Block 2) FF7E0002h
008E0002h
T_MINUS05_LK Top Block [-5] Lock Register (Block 1) FF7D0002h 008D0002h
T_MINUS06_LK Top Block [-6] Lock Register (Block 0) FF7C0002h 008C0002h
GPI_REG
General Purpose Input Register
FF7C0100h 008C0100h
Note: 1. This map is referred to the boot memory (ID0-ID3 floating or driven, Low).
Default
Value
01h
01h
01h
01h
01h
01h
01h
N/A
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
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