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HCPL-257K-100 Ver la hoja de datos (PDF) - HP => Agilent Technologies

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HCPL-257K-100 Datasheet PDF : 12 Pages
First Prev 11 12
IF
B
RM
A
D.U.T.
VCC
+5 V
RL
VO
VFF
GND
SINGLE CHANNEL OR
COMMON VCC DEVICES
VCM
+
PULSE GEN.
NOTE: BASE LEAD NOT CONNECTED.
Figure 10. Test Circuit for Transient Immunity and Typical Waveforms.
5V
VCC
220
TTL
D.U.T.
RL
VCC
GND
EACH CHANNEL
LOGIC GATE
0.01 µF
Figure 11. Recommended Logic Interface.
Logic Family
LSTTL
CMOS
Device No.
54LS14 CD40106BM
VCC
5V
5 V 15 V
RL 5% Tolerance 18 k* 8.2 k22 k
*The equivalent output load resistance is affected by the
LSTTL input current and is approximately 8.2 k.
This is a worst case design which takes into account 25%
degradation of CTR. See App. Note 1002 to assess actual
degradation and lifetime.
(EACH INPUT)
+–
VIN
D.U.T.*
VCC
VO
GND
VCC
VOC
0.1 µF
(EACH OUTPUT)
NOMINAL CONDITIONS
PER CHANNEL: IF = 20 mA
IO = 4 mA
ICC = 30 µA
NOTE: BASE LEAD NOT CONNECTED.
TA = +125 °C
Figure 12. Operating Circuit for Burn-In and Steady State
Life Tests. All Channels Tested Simultaneously.
1-569

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