PCF8594C-2T Ver la hoja de datos (PDF) - Integrated Circuit Systems

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PCF8594C-2T

256 to 1024×8-bit CMOS EEPROMs with I2C-bus interface

Integrated Circuit Systems 

Philips Semiconductors

256 to 1024 × 8-bit CMOS EEPROMs with

I2C-bus interface

Product specification

PCF85xxC-2 family

12 WRITE CYCLE LIMITS

Selection of the chip address is achieved by connecting the A0, A1 and A2 inputs to either VSS or VDD.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP. MAX. UNIT

E/W cycle timing

tE/W

E/W cycle time

internal oscillator

external clock

−

7

−

ms

4

−

10

ms

Endurance

NE/W

E/W cycle per byte

Tamb = −40 to +85 °C

Tamb = 22 °C

100000 −

−

−

1000000 −

cycles

cycles

13 EXTERNAL CLOCK TIMING

handbook, full pagewidth

PTC

SDA

SCL

td t r t HIGH t f t LOW

1

2

257

STOP

Fig.11 One byte E/W cycle.

MBA697

handbook, full pagewidth

PTC

SDA

SCL

td t r t HIGH t f t LOW

1

2

n x 256 + 1

STOP

Fig.12 n bytes E/W cycle (n = 2 to 7).

MBA698

1997 Feb 13

14

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