OX12PCI840-PQC60-A Ver la hoja de datos (PDF) - Oxford Semiconductor
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OX12PCI840-PQC60-A Datasheet PDF : 33 Pages
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OXFORD SEMICONDUCTOR LTD.
5.3.10 Configuration B register
ECR[7:5] must be set to ‘111’ to access this register. Read
only, all bits will be set to 0, except for bit[6] which will
reflect the state of the interrupt.
5.3.11 Extended control register ‘ECR’
The Extended control register is located at offset 002h in
upper block. It is used to configure the operation of the
parallel port.
ECR[4:0]: Reserved - write
These bits are reserved and must always be set to
“00001”.
ECR[0]: Empty - read
When DCR[5} = ‘0’
logic 0 ⇒ FIFO contains at least one byte
logic 1 ⇒ FIFO completely empty
When DCR[5} = ‘1’
logic 0 ⇒ FIFO contains at least one byte
logic 1 ⇒ FIFO contains less than one byte
ECR[1]: Full - read
When DCR[5} = ‘0’
OX12PCI840
logic 0 ⇒ FIFO has at least one free byte
FIFO completely full
When DCR[5} = ‘1’
logic 0 ⇒ FIFO has at least one free byte
logic 1 ⇒ FIFO full
ECR[2]: serviceIntr - read
When DCR[5} = ‘0’
logic 1 ⇒ writeIntrThreshold (8) free bytes or more in
FIFO
When DCR[5} = ‘1’
logic 1 ⇒ readIntrThreshold (8) bytes or more in FIFO
ECR[7:5]: Mode – read / write
These bits define the operational mode of the parallel port.
logic ‘000’
SPP
logic ‘001’
PS2
logic ‘010’
Reserved
logic ‘011’
ECR
logic ‘100’
EPP
logic ‘101’
Reserved
logic ‘110’
Test
logic ‘111’
Config
DS-0021 Jun 05
Page 21
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