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NT5SV16M4DT

64Mb Synchronous DRAM

Unspecified 

NT5SV16M4DT

NT5SV8M8DT

NT5SV4M16DT

64Mb Synchronous DRAM

Operating, Standby, and Refresh Currents (TA = 0 to +70°C, VDD = 3.3V ±0.3V)

Parameter

Symbol

Test Condition

Operating Current

Precharge Standby Current

in Power Down Mode

Precharge Standby Current

in Non-Power Down Mode

No Operating Current

(Active state: 4 bank)

Operating Current (Burst

Mode)

Auto (CBR) Refresh Current

Self Refresh Current

ICC1

ICC2P

ICC2PS

ICC2N

ICC2NS

ICC3N

ICC3P

ICC4

ICC5

ICC6

1 bank operation

tRC = tRC(min), tCK = min

Active-Precharge command cycling

without burst operation

CKE ≤ VIL(max), tCK = min,

CS = VIH(min)

CKE ≤ VIL(max), tCK = Infinity,

CS = VIH(min)

CKE ≥ VIH(min), tCK = min,

CS = VIH (min)

CKE ≥ VIH(min), tCK = Infinity,

CKE ≥ VIH(min), tCK = min,

CS = VIH (min)

CKE ≤ VIL(max), tCK = min,

tCK = min,

Read/ Write command cycling,

Multiple banks active, gapless data,

BL = 4

tCK = min, tRC = tRC(min)

CBR command cycling

CKE ≤ 0.2V

-6K

(6ns)

60

75

120

-7K

(7ns)

-7

(7ns)

Units Notes

55

mA 1, 2, 3

1

1

10

5

30

9

70

mA

1

mA

1

mA

1, 5

mA

1, 7

mA

1, 5

mA

1, 6

mA 1, 3, 4

110

1

mA

1

mA

1

1. Currents given are valid for a single device. The total current for a stacked device depends on the operation being performed

on the other deck.

2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC.

Input signals are changed up to three times during tRC(min).

3. The specified values are obtained with the output open.

4. Input signals are changed once during tCK(min).

5. Input signals are changed once during three clock cycles.

6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).

7. Input signals are stable.

REV 1.1

10/01

15

© NANYA TECHNOLOGY CORP. All rights reserved.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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