ML6553 Ver la hoja de datos (PDF) - Fairchild Semiconductor

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Fabricante

ML6553

Bus Termination Regulator

Fairchild Semiconductor 

ML6553

PRODUCT SPECIFICATION

Functional Description

The ML6553 switching regulator is designed to sink and

source 1A load current and maintain a tight output voltage

regulation without the need for external feedback. Feedback

is accomplished internally by setting the average value of VL

equal to VCCQ/2 through a high gain error amp. The

ML6553 implements an open loop design that does not

require external loop compensation, providing a simplified

regulator design that can be used in cost sensitive applica-

tions.

Regulator Operation

Refer to the block diagram on the first page of this datasheet.

The oscillator/ramp block generates a 650kHz clock pulse

that is used to set the flip-flop. It also generates a 650kHz

ramp that the PWM comparator uses to reset the flip-flop.

When the flip-flop is set, the high side switch (Q1) is turned

on and the low side switch (Q2) is held off. In this state, the

voltage at VL is pulled up to PVDD, which the error amp,

integrates and inverts. The resulting output voltage of the

error amp will decline until it intersects the rising voltage of

the ramp. When this occurs the flip-flop is reset. In the reset

state, the high side switch is off, the low side switch is on

and VL is pulled to DGND. The flip-flop will remain in the

reset state until the next clock pulse. A timing diagram is

shown in Figure 1.

In the absence of a load, the duty cycle will be 50% if the

PVDD and VCCQ are the same. The average voltage at VL

will be half the voltage applied to VCCQ, and the net current

change will be zero. If the ML6553 needs to source current,

the duty cycle will increase, resulting in more current being

supplied to the load. If the ML6553 needs to sink current, the

duty will decrease, resulting in current being pulled from the

load and returned back to the PVDD supply.

VL

RAMP

VINTEG

PWMCMP

CLK

Q

4

Figure 1. Timing Diagram

REV. 1.0.2 3/21/01

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