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MC1151A

Advanced Step Motor Control Chipset

PMD 

Pin Descriptions

The following tables provide pin descriptions for the MC1401 and MC1401-P series chipsets.

IC

Pin Name

Pin #

I/O Chip Pinouts

I/O

Pulse1

28

Pulse2

26

Pulse3

40

Pulse4

39

I/O

Dir1

42

Dir2

30

Dir3

35

Dir4

34

I/O

~Home1

13

~Home2

23

~Home3

11

~Home4

10

Description/Functionality

Pulse signal for channels 1-4 (output). This signal is always a square wave, regardless of

pulse rate. Nominal 'step' occurs when signal goes from a high state to a low state.

NOTE: For MC1451A all 4 pins are valid. For MC1251A pins for axes 1 & 2 only are valid.

For MC1151A pins for axis 1 only are valid. Invalid axis pins can be left unconnected.

Direction signal for channels 1-4 (output). This signal indicates the direction of motion, and

works in conjunction with the pulse signal. A high level on this signal indicates a positive

direction move, and a low level indicates a negative direction move.

NOTE: For MC1451A all 4 pins are valid. For MC1251A pins for axes 1 & 2 only are valid.

For MC1151A pins for axis 1 only are valid. Invalid axis pins can be left unconnected.

Home signals for axis 1-4 (input). Each of these signals provide a general purpose input to

the external breakpoint mechanism. Using these signals it is possible to stop, start, or alter

the motion trajectory. See theory of operations for details.

An active home signal is recognized by the chipset as a low state.

I/O

CPClk

46

I/O

I/OClkIn

52

I/O

I/OClkOut

45

I/O

CPAddr0

68

CPAddr1

27

CPAddr2

29

CPAddr3

12

I/O

~CPWrite

2

I/O

CPCntrl0

20

CPCntrl1

36

CPCntrl2

22

CPCntrl3

63

I/O

HostCmd

41

I/O

HostRdy

37

NOTE: For MC1451A all 4 pins are valid. For MC1251A pins for axes 1 & 2 only are valid.

For MC1151A pin for axis 1 only is valid. Invalid axis pins can be left unconnected.

I/O chip clock (input). This signal is connected directly to the ClkOut pin (CP chip) and

provides the clock signal for the I/O chip. The frequency of this signal is 1/4 the user-provided

ClkIn (CP chip) frequency.

Phase shifted clock (input). This signal is connected to I/OClkOut (I/O chip), and inputs a

phase shifted clock signal.

Phase shifted clock (output). This signal is connected to I/OClkIn (I/O chip), and outputs a

phase shifted clock signal.

I/O chip to CP chip communication address (input). These 4 signals are connected to the

corresponding I/OAddr0-3 pins (CP chip), and together provide addressing signals to

facilitate CP to I/O chip communication.

I/O chip to CP chip communication write (input). This signal is connected to the ~I/OWrite pin

(CP chip) and provides a write strobe to facilitate CP to I/O chip communication.

I/O chip to CP chip communication control (mixed). These 4 signals are connected to the

corresponding I/OCntrl0-3 pins (CP chip), and provide control signals to facilitate CP to I/O

chip communication.

Host Port Command (input). This signal is asserted high to write a host command to the chip

set. It is asserted low to read or write a host data word to the chipset

Host Port Ready/Busy (output). This signal is used to synchronize communication between

the DSP and the host. HostRdy will go low (indicating host port busy) at the end of a host

command write or after the second byte of a data write or read. HostRdy will go high

(indicating host port ready) when the command or data word has been processed and the

chip set is ready for more I/O operations. All host port communications must be made with

HostRdy high (indicating ready).

Typical busy to ready cycle is 82.5 uSec..

13

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