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M34512M2-XXXFP

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MITSUBISHI ELECTRIC  

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MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(7) Interrupt sequence

Interrupts only occur when the respective INTE flag, interrupt en-

able bits (V10–V13 and V20–V23), and interrupt request flag are

“1.” The interrupt actually occurs 2 to 3 machine cycles after the

cycle in which all three conditions are satisfied. The interrupt oc-

curs after 3 machine cycles only when the three interrupt condi-

tions are satisfied on execution of other than one-cycle instructions

(Refer to Figure 16).

When an interrupt request flag is set after its interrupt is enabled (Note 1)

f (XIN) (middle-speed mode)

f (XIN) (high-speed mode)

System clock

Interrupt enable

flag (INTE)

1 machine cycle

T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3

T1 T2 T3

EI instruction

execution cycle

Interrupt enabled state

Interrupt disabled state

External

interrupt

INT0, INT1

EXF0, EXF1

Timer 1,

Timer 2,

Timer 3,

Timer 4,

A-D, and

Serial I/O

interrupts

T1F, T2F, T3F,

T4F, ADF,SIOF

Retaining level of system

clock for 4 periods or more

is necessary.

Interrupt activated

condition is satisfied.

Flag cleared

2 to 3 machine cycles

(Notes 2, 3)

The program starts from

the interrupt address.

Notes 1: The 4512 Group operates in the middle-speed mode after system is released from reset.

2: The address is stacked to the last cycle.

3: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.

Fig. 16 Interrupt sequence

16

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