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M2S28D20ATP

128M Double Data Rate Synchronous DRAM

MITSUBISHI ELECTRIC  

DDR SDRAM (Rev.0.1)

Jun,'00 Preliminary

MITSUBISHI LSIs

M2S28D20/ 30/ 40ATP

128M Double Data Rate Synchronous DRAM

AC TIMING REQUIREMENTS(Continues)

(Ta=0 ~ 70oC, Vdd = VddQ = 2.5V +0.2V, Vss = VssQ = 0V, unless otherwise noted)

Symbol

AC Characteristics Parameter

tRAS Row Active time

tRC Row Cycle time(operation)

tRFC Auto Ref. to Active/Auto Ref. command period

tRCD Row to Column Delay

tRP Row Precharge time

tRRD Act to Act Delay time

tWR Write Recovery time

tDAL Auto Precharge write recovery + precharge time

tWTR Internal Write to Read Command Delay

tXSNR Exit Self Ref. to non-Read command

tXSRD Exit Self Ref. to -Read command

tXPNR Exit Power down to command

tXPRD Exit Power down to -Read command

tREFI Average Periodic Refresh interval

-75

-10

Unit

Min.

Max

Min.

Max

45 120,000 50 120,000 ns

65

70

ns

75

80

ns

20

20

ns

20

20

ns

15

15

ns

15

15

ns

35

35

ns

1

1

tCK

75

80

ns

200

200

tCK

1

1

tCK

1

1

tCK

15.6

15.6

µs

Notes

18

17

Output Load Condition

VOUT

VTT =VREF

50Ω

Zo=50Ω

30pF

VREF

DQS

DQ

Output Timing

Measurement

Reference Point

VREF

VREF

MITSUBISHI ELECTRIC

19

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