LT1789CS8-10-PBF Ver la hoja de datos (PDF) - Linear Technology

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LT1789CS8-10-PBF

Micropower, Single Supply Rail-to-Rail Output Instrumentation Amplifiers

Linear Technology 

LT1789-1/LT1789-10

BLOCK DIAGRAM

V+

+IN 3

5.7k

RG 1

V–

–IN 2

V+

RG 8

5.7k

V–

V+

100k

–

A1

+

V–

VB

V+

100k

–

A2

+

V–

VB

R1

R2

110k/10k* 110k/100k*

+

A3

–

R3

R4

110k/10k* 110k/100k*

*LT1789-1/LT1789-10

Figure 1. Block Diagram

V+

5 REF

V–

V+

6 OUT

7 V+

V–

4 V–

1789 F01

APPLICATIONS INFORMATION

Setting the Gain

The gain of the LT1789-1 and LT1789-10 is set by the

value of resistor RG, applied across pins 1 and 8. For the

LT1789-1, the gain G will be:

G = 1+ 200k/RG

and RG can be calculated from the desired gain by

RG = 200k/(G – 1)

For the LT1789-10, the gain G will be

G =10 • (1 + 200k/RG)

and RG can be calculated from the desired gain by

RG = 200k/(0.1 • G – 1)

For the lowest achievable gain, RG may be set to infinity

by leaving Pins 1 and 8 open.

Input and Output Offset Voltage

The offset voltage of the LT1789-1/LT1789-10 has two

components: the output offset and the input offset. The

total offset voltage referred to the input (RTI) is found by

dividing the output offset by the programmed gain (G) and

adding it to the input offset. At high gains the input offset

voltage dominates, whereas at low gains the output offset

voltage dominates. The total offset voltage is:

Total input offset voltage (RTI)

= input offset + (output offset/G)

Total output offset voltage (RTO)

= (input offset • G) + output offset

1789fc

18

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