GM5060 Ver la hoja de datos (PDF) - Unspecified

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GM5060

GRAPHICS PROCESSING IC PROVIDING HIGH QUALITY IMAGES FOR LCD MONITORS

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Genesis Microchip

gm5060 / gm5060-H Data Sheet

Name

DBGRN3

DBGRN2

DBGRN1

DBGRN0

DBBLU7

DBBLU6

DBBLU5

DBBLU4

DBBLU3

DBBLU2

DBBLU1

DBBLU0

Name

FSCLK

FSCKE

FSRAS

FSCAS

FSWE

FSDQM3

FSDQM2

FSDQM1

FSDQM0

FSADDR13

FSADDR12

FSADDR11

FSADDR10

FSADDR9

FSADDR8

FSADDR7

FSADDR6

FSADDR5

FSADDR4

FSADDR3

FSADDR2

FSADDR1

FSADDR0

I/O

O

Ball# Description

A19

A20

B19

B20

C19

Display output blue data (odd or right pixel).

C20

[Tri-state output, programmable drive 0-24mA, not 5V-tolerant]

D18

D19

D20

E18

E19

E20

Table 7. Frame Store Interface Signals

I/O Ball# Description

O

T3

SDRAM clock. This signal is rising edge active.

[Tri-state output, Programmable Drive 0-24mA, not 5V-tolerant]

O

U1

SDRAM clock enable. This signal is active high.

[Tri-state output, 8mA drive, 5V-tolerant]

O

V1

SDRAM row address strobe. This signal is active low

[Tri-state output, 8mA drive, 5V-tolerant]

O

U3

SDRAM column address strobe. This signal is active low.

[Tri-state output, 8mA drive, 5V-tolerant]

O

U2

SDRAM write enable. This signal is active low.

[Tri-state output, 8mA drive, 5V-tolerant]

O

W12 SDRAM data masks. Each bit enables one of four SDRAM byte “lanes”. This allows host OSD access

V12

to the SDRAM to be byte oriented. This signal is active high.

Y8

Bit 0 enables FSDATA(7:0).

W8

Bit 1 enables FSDATA(15:8).

Bit 2 enables FSDATA(23:16).

Bit 3 enables FSDATA(31:24).

[Tri-state output, 8mA drive, 5V-tolerant]

IO

V2

SDRAM multiplexed address bus.

W1

FSADDR[13:0] are used for bootstrapping configuration. See Section 4.17.

Y1

[Bidirectional, 8mA drive output, 5V-tolerant]

W2

Y2

V3

W3

Y3

V4

W4

Y4

V5

W5

Y5

February 2002

9

C5060-DAT-01G

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