FM4005
AC Test Conditions
Input Pulse Levels
Input rise and fall times
Input and output timing levels
0.1 VDD to 0.9 VDD
10 ns
0.5 VDD
Diagram Notes
All start and stop timing parameters apply to both read and write
cycles. Clock specifications are identical for read and write cycles.
Write timing parameters apply to slave address, word address, and
write data bits. Functional relationships are illustrated in the relevant
data sheet sections. These diagrams illustrate the timing parameters
only.
Equivalent AC Load Circuit
5.5V
Output
1700 Ω
100 pF
Read Bus Timing
SCL
tR
t HIGH
` tF
tLOW
t SP
t SP
t SU:STA
tBUF
SDA
1/fSCL
t HD:DAT
tSU:DAT
Start
Stop Start
tAA
t DH
Acknowledge
Write Bus Timing
SCL
SDA
tSU:STO
tHD:STA
Start
Stop Start
tHD:DAT
tSU:DAT
tAA
Acknowledge
Rev. 2.3
Oct. 2006
Page 21 of 23