PSD834F2-10J Ver la hoja de datos (PDF) - STMicroelectronics

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PSD834F2-10J

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

Pin Name Pin Type

Description

These pins make up Port A. These port pins are configurable and can have the following

functions:

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

29

28

27

25

24

23

22

21

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellAB0-7) outputs.

3. Inputs to the PLDs.

4. Latched address outputs (see Table 5).

I/O 5. Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA

in burst mode.

6. As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.

7. D0/A16-D3/A19 in M37702M2 mode.

8. Peripheral I/O mode.

Note: PA0-PA3 can only output CMOS signals with an option for high slew rate. However,

PA4-PA7 can be configured as CMOS or Open Drain Outputs.

PB0

7

These pins make up Port B. These port pins are configurable and can have the following

PB1

6

functions:

PB2

5

1. MCU I/O – write to or read from a standard output or input port.

PB3

PB4

4

3

I/O

2. CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.

3. Inputs to the PLDs.

PB5

2

4. Latched address outputs (see Table 5).

) PB6

52

Note: PB0-PB3 can only output CMOS signals with an option for high slew rate. However,

t(s PB7

51

PB4-PB7 can be configured as CMOS or Open Drain Outputs.

c PC0 pin of Port C. This port pin can be configured to have the following functions:

u 1. MCU I/O – write to or read from a standard output or input port.

d 2. CPLD macrocell (McellBC0) output.

ro PC0

20

I/O 3. Input to the PLDs.

P 4. TMS Input2 for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

te PC1 pin of Port C. This port pin can be configured to have the following functions:

le 1. MCU I/O – write to or read from a standard output or input port.

o 2. CPLD macrocell (McellBC1) output.

s PC1

19

I/O 3. Input to the PLDs.

b 4. TCK Input2 for the JTAG Serial Interface.

O This pin can be configured as a CMOS or Open Drain output.

) - PC2 pin of Port C. This port pin can be configured to have the following functions:

t(s 1. MCU I/O – write to or read from a standard output or input port.

PC2

18 I/O 2. CPLD macrocell (McellBC2) output.

c 3. Input to the PLDs.

u This pin can be configured as a CMOS or Open Drain output.

rod PC3 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

P 2. CPLD macrocell (McellBC3) output.

te PC3

17

I/O 3. Input to the PLDs.

4. TSTAT output2 for the JTAG Serial Interface.

le 5. Ready/Busy output for parallel In-System Programming (ISP).

o This pin can be configured as a CMOS or Open Drain output.

bs PC4 pin of Port C. This port pin can be configured to have the following functions:

O 1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC4) output.

PC4

14

I/O 3. Input to the PLDs.

4. TERR output2 for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

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