MBM29DL164BD90PFTR Ver la hoja de datos (PDF) - Fujitsu
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MBM29DL164BD90PFTR Datasheet PDF : 76 Pages
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MBM29DL16XTD/BD-70/90/12
• Write/Erase/Program Operations
Parameter Symbols
JEDEC Standard
Description
70
90
12 Unit
tAVAV
tWC Write Cycle Time
Min. 70
90
120 ns
tAVWL
tAS Address Setup Time
Min.
0
0
0
ns
—
tASO
Address Setup Time to OE Low During
Toggle Bit Polling
Min. 12
15
15
ns
tWLAX
tAH Address Hold Time
Min. 45
45
50
ns
—
tAHT
Address Hold Time from CE or OE High
During Toggle Bit Polling
Min.
0
0
0
ns
tDVWH
tDS Data Setup Time
Min. 30
35
50
ns
tWHDX
tDH Data Hold Time
Min.
0
0
0
ns
—
tOEH
Output Enable Read
Hold Time
Toggle and Data Polling
Min.
Min.
0
10
0
10
0
ns
10
ns
—
tCEPH CE High During Toggle Bit Polling
Min. 20
20
20
ns
—
tOEPH OE High During Toggle Bit Polling
Min. 20
20
20
ns
tGHWL
tGHWL Read Recover Time Before Write
Min.
0
0
0
ns
tGHEL
tGHEL Read Recover Time Before Write
Min.
0
0
0
ns
tELWL
tCS CE Setup Time
Min.
0
0
0
ns
tWLEL
tWS WE Setup Time
Min.
0
0
0
ns
tWHEH
tCH CE Hold Time
Min.
0
0
0
ns
tEHWH
tWH WE Hold Time
Min.
0
0
0
ns
tWLWH
tWP Write Pulse Width
Min. 35
35
50
ns
tELEH
tCP CE Pulse Width
Min. 35
35
50
ns
tWHWL
tWPH Write Pulse Width High
Min. 25
30
30
ns
tEHEL
tCPH CE Pulse Width High
Min. 25
30
30
ns
tWHWH1
tWHWH1 Byte Programming Operation
Typ.
8
8
8
µs
tWHWH2
tWHWH2 Sector Erase Operation (Note 1)
Typ.
1
1
1
sec
—
tVCS VCC Setup Time
Min. 50
50
50
µs
—
tVIDR Rise Time to VID (Note 2)
Min. 500
500
500 ns
—
tVACCR Rise Time to VACC (Note 2)
Min. 500
500
500 ns
—
tVLHT Voltage Transition Time (Note 2)
Min.
4
4
4
µs
—
tWPP Write Pulse Width (Note 2)
Min. 100
100
100 µs
—
tOESP OE Setup Time to WE Active (Note 2)
Min.
4
4
4
µs
(Continued)
15
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