ADP5020(RevA) Ver la hoja de datos (PDF) - Analog Devices
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ADP5020 Datasheet PDF : 28 Pages
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Data Sheet
THEORY OF OPERATION
CIRCUIT OPERATION
The buck converters use pMOSFET as the upper switch and
nMOSFET as a synchronous rectifier. This synchronous rectifica-
tion maintains high efficiency for a wide input and output
voltage range. The voltage mode control architecture, which
features a high frequency bandwidth, provides a fast load and
line transient response. The Buck 1 regulator can deliver up to
600 mA with very tight regulation. To minimize cross conduction
and maximize efficiency, an antishoot-through circuit is imple-
mented in the gate driver. The two switching regulators operate
out of phase, reducing input ripple voltage and current.
INTERNAL COMPENSATION
The ADP5020 contains an internal compensation network. The
compensation circuit is designed to make the synchronous buck
converter stable over the input line, output load, and temperature
with specified output capacitors and inductors. In addition, the
high bandwidth control loop design allows for fast load and line
transient response.
CURRENT LIMITING AND SHORT-CIRCUIT
PROTECTION
Both buck converters and the LDO have a current limit feature
that allows the ADP5020 to protect itself and any external compo-
nents during overload and short-circuit conditions. The upper
switch pMOSFET turns off if peak current exceeds the limit.
The nMOSFET is turned on for a longer period until inductor
current drops to 0 A to prevent thermal runaway.
SYNCHRONIZATION
The device has several methods of synchronizing an external
clock with the switching regulators. If the external clock is
9.6 MHz, Bit 6 (SYNC_9P6) in the OPERATIONAL_CONTROL
register (Address 0x04) must be set to 1, and Bit 5 (SYNC_19P2)
must be set to 0. This operation divides the external clock by 3
before it is applied to the switching regulator clock. If the external
clock is 19.2 MHz, Bit 5 (SYNC_19P2) in Address 0x04 must be
set to 1, and Bit 6 (SYNC_9P6) must be set to 0. This operation
divides the external clock by 6 before it is applied to the
switching regulator clock. The synchronous clock can be dc- or
ac-coupled onto the SYNC pin. For ac coupling, Bit 4 (SYNC_AC)
in Address 0x04 is set to 1; for dc coupling, Bit 4 is set to 0.
Operational control is performed by I2C writing to Register 0x04.
I2C INTERFACE
An internal register can be accessed using a synchronous
serial interface that implements the standard I2C interface. The
ADP5020 behaves as a slave device, communicating at normal
speed (100 kHz) or fast speed (400 kHz).
ADP5020
The I2C timing specifications are shown in Table 6, and the I2C
interface timing diagram is shown in Figure 3. The 7-bit slave
address of the ADP5020 is shown in Table 10.
UNDERVOLTAGE LOCKOUT
The undervoltage lockout block contains the UVLO detector
circuits for the battery voltage level. It also contains the status
registers that are required to allow the external application
processor to determine the status of the power supplies. The
most important function of the UVLO circuit is to prevent
converter operation if the supply voltage is too low. The UVLO
falling condition (when the battery voltage decreases from the
operating range level) is set to a typical value of 2.0 V, whereas the
UVLO rising condition (when the supply voltage increases from
zero) is typically 2.2 V.
THERMAL SHUTDOWN
The thermal shutdown block (TSD) prevents device damage
if the die temperature reaches a level greater than 150°C. When
the thermal shutdown limit is reached, the regulator disables
the outputs, while waiting for the die to cool down (typically, to
30°C below the thermal shutdown threshold). There are two
distinct conditions to be considered when recovering from
a thermal shutdown condition:
• The EN pin is low. If the EN pin is low and the device is
operating in I2C command mode, the outputs remain
disabled until the application processor initializes the
parameters and performs the sequencing of the regulators.
The application processor can sense a generic failure
condition by detecting a missing acknowledge bit following
an I2C command. When a thermal shutdown condition
occurs, Bit 0 (TSD) in the OPERATIONAL_CONTROL
register (Address 0x04) is latched to 1 so that the processor
can recognize the origin of the failure when resuming from
a fault condition. When the TSD bit is set, the application
processor must clear this bit to activate the regulators. If
the TSD bit is not cleared, writing to the regulator enable
bits, Bits[7:4] (BK1_EN, BK2_EN, LDO_EN, and EN_ALL),
in the REG_CONTROL_STATUS register (Address 0x03)
has no effect. The application processor can also force Bit 0
(TSD) to 1. In this case, the operation proceeds as though
a thermal shutdown condition has occurred.
• The EN pin is high. If the EN pin is high, the device resumes
operation automatically from a thermal shutdown condition.
The device resumes performing the predefined regulator
sequence without processor intervention. Bit 0 (TSD) in the
OPERATIONAL_CONTROL register (Address 0x04) is set
to indicate that a thermal shutdown has occurred, and it is
not possible to activate the regulators using an I2C command
unless the host sets the TSD bit to 0.
Rev. A | Page 13 of 28
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