ADF7020BCPZ Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

ADF7020BCPZ

High Performance, ISM Band, FSK/ASK Transceiver IC

Analog Devices 

Data Sheet

ADF7020

Parameter

REFERENCE INPUT

Crystal Reference

External Oscillator

Load Capacitance

Crystal Start-Up Time

Input Level

ADC PARAMETERS

INL

DNL

TIMING INFORMATION

Chip Enabled to Regulator Ready

Chip Enabled to RSSI Ready

Tx to Rx Turnaround Time

LOGIC INPUTS

Input High Voltage, VINH

Input Low Voltage, VINL

Input Current, IINH/IINL

Input Capacitance, CIN

Control Clock Input

LOGIC OUTPUTS

Output High Voltage, VOH

Output Low Voltage, VOL

CLKOUT Rise/Fall

CLKOUT Load

TEMPERATURE RANGE, TA

POWER SUPPLIES

Voltage Supply

VDD

Transmit Current Consumption

−20 dBm

−10 dBm

0 dBm

10 dBm

10 dBm

Receive Current Consumption

Low Current Mode

High Sensitivity Mode

Power-Down Mode

Low Power Sleep Mode

Min

Typ

3.625

3.625

33

2.1

1.0

0.7 ×

VDD

±1

±1

10

3.0

150 µs +

(5 × TBIT)

DVDD −

0.4

−40

Max Unit

Test Conditions

24

MHz

24

MHz

pF

See crystal manufacturer’s specification sheet

ms

11.0592 MHz crystal, using 33 pF load capacitors

ms

Using 16 pF load capacitors

CMOS levels See the Reference Input section

LSB

From 2.3 V to 3.6 V, TA = 25°C

LSB

From 2.3 V to 3.6 V, TA = 25°C

µs

CREG = 100 nF

ms

See Table 11 for more details

Time to synchronized data out, includes AGC settling;

see the AGC Information and Timing section

V

0.2 × V

VDD

±1

µA

10

pF

50

MHz

V

0.4 V

5

ns

10

pF

+85 °C

IOH = 500 µA

IOL = 500 µA

2.3

14.8

15.9

19.1

28.5

26.8

19

21

0.1

3.6 V

mA

mA

mA

mA

mA

mA

mA

1

µA

All VDD pins must be tied together

FRF = 915 MHz, VDD = 3.0 V,

PA is matched to 50 Ω

Combined PA and LNA matching network as on

EVAL-ADF7020DBZx boards

VCO_BIAS_SETTING = 12

PA matched separately with external antenna

switch, VCO_BIAS_SETTING = 12

1 Higher data rates are achievable, depending on local regulations.

2 For the definition of frequency deviation, see the Register 2—Transmit Modulation Register (FSK Mode) section.

3 For the definition of GFSK frequency deviation, see the Register 2—Transmit Modulation Register (GFSK/GOOK Mode) section.

4 Measured as maximum unmodulated power. Output power varies with both supply and temperature.

5 For matching details, see the LNA/PA Matching section and the AN-764 Application Note.

6 Sensitivity for combined matching network case is typically 2 dB less than separate matching networks.

7 See Table 5 for a description of different receiver modes.

8 Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications.

Rev. D | Page 7 of 48

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