AD61009 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD61009 Datasheet PDF : 24 Pages
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AD61009
Reference
Designation
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
T1
T2
Table III. AD61009 Evaluation Board Input and Output Connections
Connector
Type
SMA
SMA
SMA
SMA
SMA
Description
Frequency
Detector Input
Power Up
LO Input
RF Input
MGC Input
SMA
IF Output
SMA
Q Output
SMA
I Output
Jumper
Ties GREF
to VMID
Jumper
Terminal Pin
Terminal Pin
Ties Power-Up
to Positive
Supply
Power Supply
Positive Input
(VPS1, VPS2)
Power Supply
Return (GND)
Coupling
DC
DC
AC
AC
DC
AC
AC
AC
NA
NA
Approximate
Signal Level
± 400 mV
CMOS Logic
Level Input
–16 dBm
(± 50 mV)
–15 dBm max
(± 54 mV)
0.4 V to 2.0 V
(3 V Supply)
(GREF = VMID)
NA
NA
NA
NA
NA
Comments
This pin needs to be biased at VMID
and ac coupled when driven by an
external signal generator.
Tied to Positive Supply by Jumper J10.
Input is terminated in 50 Ω.
Input is terminated in 50 Ω.
Jumper is set for Manual Gain Control
Input; See Table I for Control Voltage
Values.
This signal level depends on the
AD61009’s gain setting.
This signal level depends on the
AD61009’s gain setting.
This signal level depends on the
AD61009’s gain setting.
Sets gain-control Scale Factor (SF);
SF = 75/VMID in dB/V, where
VMID = VPOS/2.
Remove to test Power-Up/-Down.
DC
DC
DC
0V
2.85 V to 5.5 V
Draws 8.5 mA at midgain connection.
–22–
REV. 0
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