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ADE7755ARSRL

Energy Metering IC with Pulse Output

Analog Devices 

ADE7755

PRELIMINARY TECHNICAL DATA

Figure 7 shows two typical connections for Channel V2. The first

option uses a PT (potential transformer) to provide complete

isolation from the power line. In the second option, the

ADE7755 is biased around the neutral wire, and a resistor divider

provides a voltage signal that is proportional to the line voltage.

Adjusting the ratio of Ra, Rb, and VR is also a convenient way of

carrying out a gain calibration on the meter.

CT

Rf

PHASE NEUTRAL

؎660mV

Rf

AGND

V2P

Cf

V2N

Cf

Ra*

Cf

Rb*

VR*

؎660mV

PHASE NEUTRAL

*Ra >> Rb + VR

*Rb + VR = Rf

V2P

Rf

V2N

Cf

Figure 7. Typical Connections for Channel 2

POWER SUPPLY MONITOR

The ADE7755 contains an on-chip power supply monitor. The

Analog Supply (AVDD) is continuously monitored by the ADE7755.

If the supply is less than 4 V ± 5%, the ADE7755 will be reset.

This is useful to ensure correct device start-up at power-up and

power-down. The power supply monitor has built in hysteresis

and filtering. This gives a high degree of immunity to false trig-

gering due to noisy supplies.

In Figure 8, the trigger level is nominally set at 4 V. The toler-

ance on this trigger level is about ± 5%. The power supply and

decoupling for the part should be such that the ripple at AVDD

does not exceed 5 V ± 5% as specified for normal operation.

AVDD

5V

4V

HPF and Offset Effects

Figure 9 shows the effect of offsets on the real power calculation.

An offset on Channel 1 and Channel 2 will contribute a dc

component after multiplication. Since the dc component is

extracted by the LPF, it will accumulate as real power. If not

properly filtered, dc offsets will introduce error to the energy

accumulation. This problem is easily avoided by enabling the

HPF (i.e., Pin AC/DC is set logic high) in Channel 1. By

removing the offset from at least one channel, no error compo-

nent can be generated at dc by the multiplication. Error terms

at cos(ωt) are removed by the LPF and the digital-to-frequency

conversion (see Digital-to-Frequency Conversion section).

{ } { } ( ) ( ) Vcos ωt + VOS × Icos ωt + IOS =

( ) ( ) V

×

2

I

+ VOS

×

IOS

+ VOS

×

I cos

ωt

+ IOS × Vcos ωt

( ) +V × I × cos 2ωt

2

VOS ؋ IOS

V؋I

2

DC COMPONENT (INCLUDING ERROR TERM)

IS EXTRACTED BY THE LPF FOR REAL

POWER CALCULATION

IOS ؋ V

VOS ؋ I

0

␻

2␻

FREQUENCY – RAD/S

Figure 9. Effect of Channel Offset on the Real Power

Calculation

The HPF in Channel 1 has an associated phase response that is

compensated for on-chip. The phase compensation is activated

when the HPF is enabled and is disabled when the HPF is not

activated. Figures 10 and 11 show the phase error between chan-

nels with the compensation network activated. The ADE7755 is

phase compensated up to 1 kHz as shown. This will ensure correct

active harmonic power calculation even at low power factors.

0V

TIME

INTERNAL

RESET RESET

ACTIVE

RESET

Figure 8. On-Chip Power Supply Monitor

–12–

REV. PrA

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