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AD7751

Energy Metering IC With On-Chip Fault Detection

Analog Devices 

AD7751

Figure 7 shows two typical connections for Channel V2. The

first option uses a PT (Potential Transformer) to provide com-

plete isolation from the mains voltage. In the second option the

AD7751 is biased around the neutral wire and a resistor divider

is used to provide a voltage signal that is proportional to the line

voltage. Adjusting the ratio of Ra and Rb is also a convenient

way of carrying out a gain calibration on the meter.

CT

Rf

PHASE NEUTRAL

؎660mV

Rf

AGND

V2P

Cf

V2N

Cf

Ra

Cf

Rb

؎660mV

VR

V2P

Rf

V2N

PHASE NEUTRAL

NOTE:

Cf

Ra

Rf;

Rb + VR = Rf

Figure 7. Typical Connections for Channel 2

POWER SUPPLY MONITOR

The AD7751 contains an on-chip power supply monitor. The

analog supply (AVDD) is continuously monitored by the AD7751.

If the supply is less than 4 V ± 5%, the AD7751 will be reset.

This is useful to ensure correct device start-up at power-up and

power-down. The power supply monitor has built-in hysteresis

and filtering. This gives a high degree of immunity to false

triggering due to noisy supplies.

As can be seen from Figure 8 the trigger level is nominally set

at 4 V. The tolerance on this trigger level is about ± 5%. The

power supply and decoupling for the part should be such that

the ripple at AVDD does not exceed 5 V ± 5% as specified for

normal operation.

AVDD

5V

4V

0V

INTERNAL

RESET RESET

TIME

ACTIVE

RESET

Figure 8. On-Chip Power Supply Monitor

HPF and Offset Effects

Figure 9 shows the effect of offsets on the real-power calculation.

As can be seen from Figure 9, an offset on Channel 1 and Channel

2 will contribute a dc component after multiplication. Since this

dc component is extracted by the LPF and used to generate the

real-power information, the offsets will have contributed a constant

error to the real power calculation. This problem is easily avoided

by enabling the HPF (i.e., pin AC/DC is set logic high) in Channel

1. By removing the offset from at least 1 channel no error com-

ponent can be generated at dc by the multiplication. Error terms

at cos(ωt) are removed by the LPF and the digital-to-frequency

conversion—see Digital-to- Frequency Conversion section.

( ) ( ) Vcos(ωt) +VOS × I × cos(ωt) + IOS =

V

×

2

I

+VOS

×

IOS

+VOS

×

I

× cos(ωt )

+V

×

IOS

× cos(ωt ) + V

×

2

I

× cos(2ωt )

VOS ؋ IOS

V؋I

2

DC COMPONENT (INCLUDING ERROR TERM)

IS EXTRACTED BY THE LPF FOR REAL-

POWER CALCULATION

IOS ؋ V

VOS ؋ I

0

␻

2␻

FREQUENCY – RAD/S

Figure 9. Effect of Channel Offsets on the Real Power

Calculation

The HPF in Channel 1 has an associated phase response that is

compensated for on-chip. The phase compensation is activated

when the HPF is enabled and is disabled when the HPF is not

activated. Figures 10 and 11 show the phase-error between chan-

nels with the compensation network activated. The AD7751 is

phase compensated up to 1 kHz as shown. This will ensure correct

active harmonic power calculation even at low power factors.

0.30

0.25

0.20

0.15

0.10

0.05

0

–0.05

–0.10

0

100 200 300 400 500 600 700 800 900 1000

FREQUENCY – Hz

Figure 10. Phase Error Between Channels (0 Hz to 1 kHz)

–12–

REV. A

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