A416316B Series
Truth Table
Function
Standby
Read: Word
Read: Lower Byte
RAS UCAS LCAS WE
OE
H
H
H
L
L
L
L
L
H
L
L
H
L
H
L
Read: Upper Byte
L
L
H
H
L
Write: Word(Early)
Write: Lower Byte(Early)
L
L
L
L
X
L
H
L
L
X
Write: Upper Byte(Early)
L
L
H
L
X
Read-Write
L
L
L
H→L L→H
Fast-Page-Mode Read: Hi-Z
-First cycle
L
H→L H→L
H
H→L
-Subsequent Cycles
L
H→L H→L
H
H→L
Fast-Page-Mode Write(Early)
-First cycle
L
H→L H→L
L
X
-Subsequent Cycles
L
H→L H→L
L
X
Fast-Page-Mode Read-Write
-First cycle
L
H→L H→L H→L L→H
-Subsequent Cycles
L
H→L H→L H→L L→H
Hidden Refresh Read
L→H→L L
L
H
L
Hidden Refresh Write
L→H→L L
L
L
X
RAS -Only Refresh
L
H
H
X
X
CBR Refresh
H→L
L
L
X
X
Self Refresh (L-ver only)
H→L
L
L
X
X
Note: 1. Byte Write may be executed with either UCAS or LCAS active.
2. Byte Read may be executed with either UCAS or LCAS active.
3. Only one CAS signal ( UCAS or LCAS ) must be active.
Address
L
Row/Col.
Row/Col.
Row/Col.
Row/Col.
Row/Col.
Row/Col.
Row/Col.
I/Os
L
Data Out
I/O0-7 = Data Out
I/O8-15 = High-Z
Notes
I/O0-7 = High-Z
I/O8-15 = Data Out
Data In
I/O0-7 = Data In
I/O8-15 = X
I/O0-7 = X
I/O8-15 = Data In
Data Out → Data In 1.2
Row/Col.
Data Out
2
Col.
Data Out
2
Row/Col.
Data In
1
Col.
Data In
1
Row/Col.
Data In
1, 2
Col.
Data In
1, 2
Row/Col.
Data Out
2
Row/Col. Data In → High-Z 1
Row
High-Z
X
High-Z
3
X
High-Z
PRELIMINARY (November, 2000, Version 0.0)
4
AMIC Technology, Inc.