MG64P Ver la hoja de datos (PDF) - Oki Electric Industry
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MG64P Datasheet PDF : 22 Pages
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s MG63P/64P/65P s ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
OKI ADVANCED DESIGN CENTER CAD TOOLS
Oki’s advanced design center CAD tools include support for the following:
• Floorplanning for front-end simulation and back-end layout control
• Clock tree structures improve first-time silicon success by eliminating clock skew problems
• JTAG Boundary scan support
• Power calculation which predicts circuit power under simulation conditions to accurately model
package requirements
Vendor
Cadence
Platform
HP9000, 7xx
IBM RS6000
Sun® [2]
Operating System [1]
HP-UX
AIX
SunOS, Solaris
IKOS
Mentor Graphicsâ„¢
HP9000, 7xx,
Sun [2]
HP9000, 7xx
Sun [2]
HP-UX, SunOS, Solaris
HP-UX
SunOS, Solaris
Model Technology
Inc. (MTI)
Synopsys
(Interface to Mentor
Graphics,
VIEWLogic)
VIEWLogic
HP9000, 7xx
Sun [2]
PC
IBM RS6000
HP9000, 7xx
Sun [2]
PC
Sun [2]
HP-UX
SunOS, Solaris
Win/NTâ„¢
AIX
HP-UX
SunOS, Solaris
Windowsâ„¢, Win/NTâ„¢ [4]
SunOS, Solaris
1. Contact Oki Application Engineering for current software versions.
2. Sun or Sun-compatible.
3. Sun and HP platform only.
4. In development.
Vendor Software/Revision [1]
Composerâ„¢
Verilogâ„¢
NC-Verilogâ„¢
Veritimeâ„¢
Verifaultâ„¢
Conceptâ„¢ [3]
Leapfrogâ„¢
NSIM
Gemini/Voyager
IDEAâ„¢
QuickVHDL
QuickSim IIâ„¢
DFT Advisor
Fastscan
V-System
Design Compilerâ„¢
HDL/VHDL Compilerâ„¢
Test Compilerâ„¢
VSSâ„¢
Powerviewâ„¢
Fusion HDL
Description
Design capture
Simulation
Simulation
Timing analysis
Fault grading
Design capture
VHDL simulation
Simulation
Design capture
VHDL simulation
Logic simulation
Test synthesis
ATPG
VHDL simulation
Compilation
Design synthesis
Test synthesis
VHDL simulation
Simulation
VHDL/Verilogâ„¢ Simulation
12
Oki Semiconductor
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