VSC7130 Ver la hoja de datos (PDF) - Vitesse Semiconductor

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VSC7130

Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Dual Repeater/Retimer

for Fibre Channel and Gigabit Ethernet

Data Sheet

VSC7130

The Verilog code for the Master Controller in proprietary mode will be made available to customers in

order to ensure compatibility. This Master Controller core is designed to use either a 25MHz or a 50MHz clock

to generate a 6.25MHz SCL clock frequency with a 25% high, 75% low duty cycle (1 clock high, 3 clocks low

at 25MHz). Slower clock frequencies are also allowable.

When using the Proprietary High-Speed mode of the Two-Wire Interface, all other interface functionality is

identical to the standard Two-Wire Interface with the exception that the interface timing has changed.

Interrupt Circuitry

Interrupts are available only when the Two-Wire Interface is used, otherwise INT# will be disabled. The

INT# output is open-drain so an external pull-up resistor is needed to allow the output to achieve a valid TTL or

CMOS HIGH level. Multiple INT# outputs can be wire ORed together. INT# is a glitchless signal which is syn-

chronized to divide-by-32 REFO clock. The output of the interrupt controller prior to the output buffer is read-

able in the INTOUT register bit, bit 2 of the CHIPS-00h register.

The VSC7130 is capable of managing several different kinds of internal interrupt conditions. Each interrupt

source can be enabled independently using the registers accessible via the Two-Wire Interface. When an

enabled interrupt event occurs, the open-drain INT# output will be asserted LOW and will stay LOW until the

interrupt is cleared. The register address corresponding to the highest priority pending interrupt can be read

from ISR-F8h. This provides a relatively fast means for determining the source of the interrupt with a single

register read operation.

Please refer to the VSC7130 User’s Manual for a more complete description of the interrupt controller and

its associated register controls.

Table 3: Interrupt Status Register Addresses, Priorities and Sources

Address

(Hex)

22

2A

23

2B

6C

6D

7C

7D

F4

Priority

1 (Highest)

2

3

4

5

6

7

8

9 (Lowest)

Label

SDU0S

SDU1S

RTMR0C

RTMR1C

MATCHA0

MATCHB0

MATCHA1

MATCHB1

TEST4

Function

SDU0 Status Register: SDR0 (7), SDF0 (6), ASD0 (2), RLL0 (1), K280 (0)

SDU1 Status Register: SDR1 (7), SDF1 (6), ASD1 (2), RLL1 (1), K281 (0)

Retimer0 Configuration Register: UNDER0 (6), OVER0 (4), ADD0 (2), DROP0 (0)

Retimer1 Configuration Register: UNDER1 (6), OVER1 (4), ADD1 (2), DROP1 (0)

Ordered Set Match Register A for CDR0: All Bits except RES (1)

Ordered Set Match Register B for CDR0: All Bits except RES (6)

Ordered Set Match Register A for CDR1: All Bits except RES (1)

Ordered Set Match Register B for CDR1: All Bits except RES (6)

Test Register 4: TESTINT (4) for diagnostics

Interrupt

Controller

Figure 10: Block Diagram of Interrupt Output

INTOUT

(CHIPS-00h, bit 2)

VDD

INT#

Shared by Other

Devices

Page 12

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

G52297-0, Rev 4.0

04/02/01

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