VSC7130RC(2000) Ver la hoja de datos (PDF) - Vitesse Semiconductor
Número de pieza
componentes Descripción
Fabricante
VSC7130RC
(Rev.:2000)
(Rev.:2000)
Vitesse Semiconductor
VSC7130RC Datasheet PDF : 22 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7130
Dual Repeater/Retimer
for Fibre Channel and Gigabit Ethernet
Pin #
35
34
36
9
10
13
46
20
32
16, 17
43
42
6, 5, 4, 3, 2
44
1
30
37
33
14
12, 29, 38
41, 47
8, 11
21, 24
55, 58
18
15
7, 19, 25 28,
45, 49, 52
59, 62, 64
53, 54, 63
Name
MODE0
MODE1
HALF/FULL
REFO+
REFO-
SDET
RXBIAS
T/R
BYP
CAP0, CAP1
SDA
SCL
A0-A4
TWI
TWO
INT#
TEST0
TEST1
TEST2
VDD
VDDP
VDDA
VSSA
Description
INPUT - TTL. Selects the mode. 00=Dual Repeater, 01=Hub, 10=GBIC, 11=reserved.
Overridden by the MODEDIS register bit.
INPUT - TTL. When LOW, REFI is 1/10th the baud rate. When HIGH, REFI is 1/20th
the baud rate
OUTPUT - PECL: This is a buffered version of REFI+/- which is intended for daisy
chaining the reference clocks between multiple chips.
BIDIRECTIONAL - TTL: Configured by default as an input intended to be connected to
the LOS from an optics module. Can be configured as an output via the Two-Wire
Interface so the protocol device can determine if valid data is present.
INPUT - ANALOG: An external resistor to ground sets the level of the analog signal
detect circuits in the RX0+/-, RX1+/- and SI+/- inputs.
INPUT - TTL. When HIGH, CDR0 is configured as a Retimer, when LOW, a Repeater.
Overridden by T/RDIS.
INPUT - TTL. When HIGH, MUX3 passes SI to SO. When LOW, MUX3 passes the
output of CDR1 to SO. Overridden by BYPDIS.
Clock Multiplier Unit PLL Loop Filter Capacitor. Nominally 0.1 uF, +/-20%, X7R
BIDIRECTIONAL - TTL: This is the Two-Wire Interface data pin
INPUT - TTL: This is the Two-Wire Interface serial clock input. For normal Two-Wire
Interface usage, SCL may be clocked at up to 400 KHz. For Proprietary Link mode, SCL
should be at REFI/8 (HALF/FULL is HIGH) or REFI/16 (HALF/FULL is LOW).
INPUT - TTL: A4 is the address to select the group address for Two-Wire Interface
addressing. A0-A3 select the Two-Wire Interface address. A0-A3 are active only if TWI
is LOW.
INPUT - TTL: Two-Wire Interface Input. This input enables daisy chaining of devices
on the Two-Wire Interface so that addresses can be assigned in software.
OUTPUT - TTL: Two-Wire Interface Output. This output enables daisy chaining of
devices on the Two-Wire Interface so that addresses can be assigned in software.
OUTPUT - TTL (Open Drain): This output indicates that an interruptible condition
occurred internally.
INPUT - TTL. LOW for factory test, HIGH for normal operation.
Power Supply. 3.3V Supply.
High-Speed Output Power Supply. Pins 8 and 11 are for REFO+/- and may be left
unconnected in order to power down this output buffer. Pins 21 and 24 are for SO+/-.
Pins 55 and 58 are for TX+/-
Analog Power Supply. 3.3V for Clock Multiplier PLL. Bypass to VSSA
Analog Ground
VSS
Ground.
N/C
Do not connect. (These are internally connected).
G52297-0, Rev. 2.3
1/17/00
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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