CY7C68053-56BAXI Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C68053-56BAXI Datasheet PDF : 42 Pages
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CY7C68053
Table 6. Strap Boot EEPROM Address Lines to These
Values
Bytes Example EEPROM A2
A1
A0
16
24AA00[8]
N/A N/A N/A
128
24AA01
0
0
0
256
24AA02
0
0
0
4K
24AA32
0
0
1
8K
24AA64
0
0
1
16K
24AA128
0
0
1
3.18.2 I2C Interface Boot Load Access
At power on reset the I2C interface boot loader loads the
VID/PID/DID and configuration bytes and up to 16 kBytes of
program/data. The available RAM spaces are 16 kBytes from
0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The 8051
is reset. I2C interface boot loads only occur after power on reset.
3.18.3 I2C Interface General Purpose Access
The 8051 can control peripherals connected to the I2C bus using
the I2CTL and I2DAT registers. FX2LP18 provides I2C master
control only, it is never an I2C slave.
4. Pin Assignments
Figure 6 identifies all signals for the package. It is followed by the
pin diagram.Three modes are available: Port, GPIF master, and
Slave FIFO. These modes define the signals on the right edge
of the diagram. The 8051 selects the interface mode using the
IFCONFIG[1:0] register bits. Port mode is the power on default
configuration.
Figure 6. Signals
Port
XTALIN
XTALOUT
RESET#
WAKEUP#
SCL
SDA
IFCLK
CLKOUT
DPLUS
DMINUS
GPIF Master
PD7 FD[15]
PD6 FD[14]
PD5 FD[13]
PD4 FD[12]
PD3 FD[11]
PD2 FD[10]
PD1 FD[9]
PD0 FD[8]
PB7 FD[7]
PB6 FD[6]
PB5 FD[5]
PB4 FD[4]
PB3 FD[3]
PB2 FD[2]
PB1 FD[1]
PB0 FD[0]
RDY0
RDY1
CTL0
CTL1
CTL2
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
Slave FIFO
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
SLRD
SLWR
FLAGA
FLAGB
FLAGC
INT0#/PA0
INT1#/PA1
SLOE
WU2/PA3
FIFOADR0
FIFOADR1
PKTEND
PA7/FLAGD/SLCS#
Note
8. This EEPROM does not have address pins.
Document # 001-06120 Rev *J
Page 11 of 42
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