74F109SJ Ver la hoja de datos (PDF) - Fairchild Semiconductor

Número de pieza

componentes Descripción

Fabricante

74F109SJ

Dual JK Positive Edge-Triggered Flip-Flop

Fairchild Semiconductor 

Truth Table

Inputs

Outputs

SD

CD

CP

J

K

Q

Q

L

H

X

X

X

H

L

H

L

X

X

X

L

H

L

H

H

H

H

L

H

H

H

H

X

X

I

h

I

h

X

I

I

h

h

H

H

L

H

Toggle

Q

Q

H

L

H

H

L

X

X

Q

Q

H (h) = HIGH Voltage Level

L (l) = LOW Voltage Level

= LOW-to-HIGH Transition

X = Immaterial

Q0 (Q0) = Before LOW-to-HIGH Transition of Clock

Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition.

Unit Loading/Fan Out

Pin Names

Description

U.L.

Input IIH/IIL

HIGH/LOW Output IOH/IOL

J1, J2, K1, K2 Data Inputs

CP1, CP2

Clock Pulse Inputs (Active Rising Edge)

CD1, CD2

Direct Clear Inputs (Active LOW)

SD1, SD2

Direct Set Inputs (Active LOW)

Q1, Q2, Q1, Q2 Outputs

1.0/1.0

1.0/1.0

1.0/3.0

1.0/3.0

50/33.3

20 µA/−0.6 mA

20 µA/−0.6 mA

20 µA/−1.8 mA

20 µA/−1.8 mA

−1 mA/20 mA

Block Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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