XE1205I074TRLF Ver la hoja de datos (PDF) - Semtech Corporation

Número de pieza

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Fabricante

XE1205I074TRLF

180 MHz – 1GHz Low-Power, High Link Budget Integrated UHF Transceiver

Semtech Corporation 

XE1205

5.3 TRANSMITTER SECTION

The XE1205 is set to transmit mode when MCParam_Select_mode is low by setting MCParam_Chip_mode(1:0) to “10”.

If MCParam_Select_mode is high the XE1205 is set to transmit mode by setting pins SW(1:0) to “10”.

The data directly modulates the LO, or an (optional) pulse shaping filter can be used resulting in an adjacent channel

power down to -37dBm at 25kHz for an output power up to 10dBm.

In continuous mode the transmitted data is sent directly to the frequency synthesizer.

In buffered mode the data is first written into the sixteen byte FIFO via the SPI interface; data from the FIFO is used to

modulate the frequency synthesizer.

5.3.1 Output power

The output power of the power amplifier is programmable on four values with the register TXParam_Power (please refer

to section 7.2.4 below), as shown in Table 10, where RFOP values are given in the Electrical Specifications section

4.2.2.

TXParam_POWER

00

01

10

11

Output power

RFOP1

RFOP2

RFOP3

RFOP4

Table 10: Output power settings

5.3.2 Transmitter in continuous mode

The transmitter works in continuous mode if the bit MCParam_Buffered_mode is low. The transmit data should be

applied to pin DATA if register bit Data_unidir is low or pin NSS_DATA if register bit Data_unidir is high. Figure 11 shows

the transmitter chain in continuous mode:

0

modulator

1

TXParam_Filter

MCParam_Data_unidir

Data shaping

filter

datain

DATA

0

NSS_DATA

1

IRQ_1

Figure 11: Transmitter data path in continuous mode

The pulse shaping function is enabled by setting TXParam_Filter to ‘1’. If the filtering option is selected, the DCLK signal

is used as data clock in the transmission and this clock is generated at a frequency according to the selected bit rate.

The DCLK signal is supplied to the microcontroller via the pin IRQ_1 which must update the data on the falling edge. The

data is sampled at the rising edge of DCLK and filtered.

Figure 12 shows an example of filtered data for a bit rate of 4.8kbit/s and a frequency deviation of 5 kHz:

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