WM8602 Ver la hoja de datos (PDF) - Wolfson Microelectronics plc
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WM8602 Datasheet PDF : 46 Pages
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CONTROL INTERFACE TIMING – 3-WIRE MODE
WM8602
CSB
SCLK
tCSL
tSCY
tSCH
tSCL
tCSH
tSCS
tCSS
SDIN
tDSU
tDHO
LSB
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data,
unless otherwise stated.
PARAMETER
Program Register Input Information
SCLK rising edge to CSB rising edge
SCLK pulse cycle time
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
CSB pulse width high
CSB rising to SCLK rising
Pulse width of spikes that will be suppressed
SYMBOL
tSCS
tSCY
tSCL
tSCH
tDSU
tDHO
tCSL
tCSH
tCSS
tps
MIN
TYP
MAX
UNIT
60
ns
80
ns
30
ns
30
ns
20
ns
20
ns
20
ns
20
ns
20
ns
2
8
ns
Table 6 Control Interface Timing – 3-Wire Serial Control Mode
w
PP Rev 1.5 May 2004
11
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