VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8169
OC-48 (FEC) 16:1 SONET/SDH
MUX with Clock Generator
Pin #
Name
I/O
35
NC
—
36
NC
—
37
NC
—
38 REF_FREQSEL
I
39
VCC
—
40
VEE
—
41
FIFO_WARN
O
42
VEE
—
43
VCC
—
44
RESET
I
45
NC
—
46
NC
—
47
NC
—
48
NC
—
49
NC
—
50
VCC
—
51
VEE
—
52
CLK16O+
O
53
CLK16O-
O
54
VCC
—
55
CLKI+
I
56
CLKI-
I
57
VEE
—
58
D0-
I
59
D0+
I
60
VCC
—
61
D1-
I
62
D1+
I
63
NC
—
64
VCC
—
65
NC
—
66
VCC
—
67
D2-
I
68
D2+
I
Level
—
—
—
TTL
+3.3V
GND
TTL
GND
+3.3V
TTL
—
—
—
—
—
+3.3V
GND
LVPECL
LVPECL
+3.3V
LVPECL
LVPECL
GND
LVPECL
LVPECL
+3.3V
LVPECL
LVPECL
—
+3.3V
—
+3.3V
LVPECL
LVPECL
Description
No connect, leave unconnected(1)
No connect, leave unconnected(1)
No connect, leave unconnected(1)
Reference clock input select
Positive power supply
Negative power supply
FIFO overflow warning
Negative power supply
Positive power supply
Reset to align FIFO Write and Read pointers
No connect, leave unconnected(1)
No connect, leave unconnected(1)
No connect, leave unconnected(1)
No connect, leave unconnected(1)
No connect, leave unconnected(1)
Positive power supply
Negative power supply
Low-speed clock output, true. A divide-by-16 version of the PLL clock.
Low-speed clock output, complement. A divide-by-16 version of the
PLL clock.
Positive power supply
Low-speed clock input for latching low-speed data, true
Low-speed clock input for latching low-speed data, complement
Negative power supply
Low-speed differential parallel data
Low-speed differential parallel data
Positive power supply
Low-speed differential parallel data
Low-speed differential parallel data
No connect, leave unconnected(1)
Positive power supply
No connect, leave unconnected(1)
Positive power supply
Low-speed differential parallel data
Low-speed differential parallel data
G52230-0, Rev 3.6
01/02/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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