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VIPER17LN Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza
componentes Descripción
Fabricante
VIPER17LN
ST-Microelectronics
STMicroelectronics ST-Microelectronics
VIPER17LN Datasheet PDF : 33 Pages
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VIPER17
7
Operation descriptions
Operation descriptions
VIPER17 is a high-performance low-voltage PWM controller chip with an 800 V, avalanche
rugged Power section.
The controller includes: the oscillator with jittering feature, the start up circuits with soft-start
feature, the PWM logic, the current limit circuit with adjustable set point, the second over
current circuit, the burst mode management, the brown-out circuit, the UVLO circuit, the
auto-restart circuit and the thermal protection circuit.
The current limit set-point is set by the CONT pin. The burst mode operation guaranties high
performance in the stand-by mode and helps in the energy saving norm accomplishment.
All the fault protections are built in auto restart mode with very low repetition rate to prevent
IC's over heating.
7.1
Power section and gate driver
The power section is implemented with an avalanche ruggedness N-channel MOSFET,
which guarantees safe operation within the specified energy rating as well as high dv/dt
capability. The Power section has a BVDSS of 800 V min. and a typical RDS(on)
of 20 Ω at 25 °C.
The integrated SenseFET structure allows a virtually loss-less current sensing.
The gate driver is designed to supply a controlled gate current during both turn-on and turn-
off in order to minimize common mode EMI. Under UVLO conditions an internal pull-down
circuit holds the gate low in order to ensure that the Power section cannot be turned on
accidentally.
7.2
High voltage startup generator
The HV current generator is supplied through the DRAIN pin and it is enabled only if the
input bulk capacitor voltage is higher than VDRAIN_START threshold, 80 VDC typically. When
the HV current generator is ON, the IDD_ch current (3 mA typical value) is delivered to the
capacitor on the VDD pin. In case of Auto Restart mode after a fault event, the IDD_ch
current is reduced to 0.6 mA, typ. in order to have a slow duty cycle during the restart phase.
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