VDP313XY Ver la hoja de datos (PDF) - Micronas

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VDP313XY

Video Processor Family

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ADVANCE INFORMATION

VDP 313xY

2.14.Serial Interface

2.14.1.I2C-Bus Interface

Communication between the VDP and the external

controller is done via I2C-bus. The VDP has two

I2C-bus slave interfaces (for compatibility with VPC/

DDP applications) - one in the front-end and one in the

back-end. Both I2C-bus interfaces use I2C clock syn-

chronization to slow down the interface if required.

Both I2C-bus interfaces use one level of subaddress:

the I2C-bus chip address is used to address the IC and

a subaddress selects one of the internal registers. The

I2C-bus chip addresses are given below:

Table 2–3: I2C Chip Addresses

Chip

A6 A5 A4 A3 A2 A1 A0 R/W

Address

front-end 1 0 0 0 1 1 1 1/0

back-end 1 0 0 0 1 0 1 1/0

The registers of the VDP have 8 or 16-bit data size;

16-bit registers are accessed by reading/writing two

8-bit data words.

Fig. 2–27 shows I2C-bus protocols for read and write

operations of the interface; the read operation requires

an extra start condition and repetition of the chip

address with read command set.

S 1000 111 W Ack

FPWR

Ack

send FP-address-

byte high

Ack

send FP-address-

byte low

Ack

P

S 1000 111 W Ack

FPDAT

Ack

send data-

byte high

Ack

send data-

byte low

Ack P

I2C write access

to FP

S 1000 111 W Ack

S 1000 111 W Ack

FPRD

FPDAT

Ack

send FP-address-

byte high

Ack

send FP-address-

byte low

Ack

P

I2C read access

to FP

Ack S 1000 111 R Ack

receive data-

byte high

receive data-

byte low

Ack

Nak P

S 1000 111 W Ack

S 1000 111 W Ack

0111 1100

0111 1100

Ack 1 or 2 byte Data P

Ack S 1000 111 R Ack high byte Data Ack

low byte Data Nak P

I2C write access

subaddress 7c

I2C read access

subaddress 7c

SDA

1

0

S

SCL

Fig. 2–27: I2C-bus protocols

W

=0

R

=1

P

Ack = 0

Nak = 1

S

= Start

P

= Stop

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