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UPSD3233

Flash Programmable System Devices with 8032 Microcontroller Core and 64 Kbit SRAM

STMicroelectronics 

uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

uPSD3200 HARDWARE DESCRIPTION

The uPSD323X Devices has a modular architec-

ture with two main functional modules: the MCU

Module and the PSD Module. The MCU Module

consists of a standard 8032 core, peripherals and

other system supporting functions. The PSD Mod-

ule provides configurable Program and Data mem-

ories to the 8032 CPU core. In addition, it has its

own set of I/O ports and a PLD with 16 macrocells

for general logic implementation. Ports A,B,C, and

D are general purpose programmable I/O ports

that have a port architecture which is different from

Ports 0-4 in the MCU Module.

The PSD Module communicates with the CPU

Core through the internal address, data bus (A0-

A15, D0-D7) and control signals (RD_, WR_,

PSEN_ , ALE, RESET_). The user defines the De-

coding PLD in the PSDsoft Development Tool and

can map the resources in the PSD Module to any

program or data address space.

Figure 15. uPSD323X Devices Functional Modules

Port 3, UART,

Intr, Timers,I2C

Port 1, Timers and

2nd UART and ADC

Port 4 PWM

and DDC

Dedicated

USB Pins

Port 3

Port 1

8032 Core

I2C

2 UARTs

Interrupt

3 Timer /

Counters

256 Byte SRAM

4

Channel

ADC

PWM

5

Channels

DDC

USB

w/ 256 Byte

&

SRAM Transceiver

Reset Logic

LVD & WDT

MCU MODULE

PSD MODULE

Page Register

Decode PLD

8032 Internal Bus

A0-A15

RD,PSEN

WR,ALE

Port 0, 2

Ext. Bus

D0-D7 Reset

1Mb or 2Mb

Main Flash

256Kb

Secondary

Flash

64Kb

SRAM

Bus

Interface

PSD Internal Bus

JTAG ISP

CPLD - 16 MACROCELLS

VCC, GND,

XTAL

Port C,

JTAG, PLD I/O

and GPIO

Port A & B, PLD

I/O and GPIO

Port D

GPIO

Dedicated

Pins

AI06619C

27/170

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