UPSD3233 Ver la hoja de datos (PDF) - STMicroelectronics
Número de pieza
componentes Descripción
Fabricante
UPSD3233
STMicroelectronics
UPSD3233 Datasheet PDF : 170 Pages
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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Table 130. CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices)
Symbol
Parameter
Conditions
Min
Max
PT Turbo Slew
Aloc Off Rate
Unit
Maximum Frequency
External Feedback
1/(tSA+tCOA)
38.4
MHz
fMAXA
Maximum Frequency
Internal Feedback (fCNTA)
1/(tSA+tCOA–10)
62.5
MHz
Maximum Frequency
Pipelined Data
1/(tCHA+tCLA)
71.4
MHz
tSA
Input Setup Time
7
+ 2 + 10
ns
tHA
Input Hold Time
8
ns
tCHA
Clock Input High Time
9
+ 10
ns
tCLA
Clock Input Low Time
9
+ 10
ns
tCOA
Clock to Output Delay
21
+ 10 – 2 ns
tARDA CPLD Array Delay
Any macrocell
11
+2
ns
tMINA
Minimum Clock Period
1/fCNTA
16
ns
Table 131. CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices)
Symbol
Parameter
Conditions
Min
Max
PT Turbo Slew
Aloc Off Rate
Unit
Maximum Frequency
External Feedback
1/(tSA+tCOA)
21.7
MHz
fMAXA
Maximum Frequency
Internal Feedback (fCNTA)
1/(tSA+tCOA–10)
27.8
MHz
Maximum Frequency
Pipelined Data
1/(tCHA+tCLA)
33.3
MHz
tSA
Input Setup Time
10
+ 4 + 20
ns
tHA
Input Hold Time
12
ns
tCHA
Clock High Time
17
+ 20
ns
tCLA
Clock Low Time
13
+ 20
ns
tCOA
Clock to Output Delay
36
+ 20 – 6 ns
tARD
CPLD Array Delay
Any macrocell
25
+4
ns
tMINA
Minimum Clock Period
1/fCNTA
36
ns
155/170
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