µPD75004, 75006, 75008
8. RESET FUNCTION
When the RESET signal is input, the µPD75008 is reset and each hardware is initialized as indicated in Table
8-1. Fig. 8-1 shows the reset operation timing.
RESET input
Wait
(31.3ms/4.19MHz)
Operation mode
or standby mode
HALT mode
Operation mode
Internal reset operation
Fig. 8-1 Reset Operation by RESET Input
Table 8-1 Status of Each Hardware after Reset (1/2)
Hardware
Program Counter (PC)
PSW
Carry Flag (CY)
Skip Flag (SK0-2)
Interrupt Status Flag (IST0)
Bank Enable Flag (MBE)
Stack Pointer (SP)
Data Memory (RAM)
General-Purpose Register
(X, A, H, L, D, E, B, C)
Bank Selection Register (MBS)
Basic Interval Counter (BT)
Timer
Mode Register (BTM)
Timer/Event
Counter
Counter (T0)
Module Register
(TMOD0)
Mode Register (TM0)
TOE0, TOUT F/F
Watch Timer Mode Register (WM)
RESET Input in Standby Mode
The contents of the lower 4 bits
of address 000H of the program
memory are set to PC11-8, and
the contents of address 001H are
set to PC7-0.
Retained
0
0
The contents of bit 7 of address
000H of the program memory is
set to MBE.
Undefined
Retained*
Retained
0
Undefined
0
0
FFH
0
0, 0
0
RESET Input during Operation
Same as at left
Undefined
0
0
Same as at left
Undefined
Undefined
Undefined
0
Undefined
0
0
FFH
0
0, 0
0
*: Data of address 0F8H to 0FDH of the data memory becomes undefined when a RESET signal is input.
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