UPD16680 Ver la hoja de datos (PDF) - NEC => Renesas Technology

Número de pieza

componentes Descripción

Fabricante

UPD16680

1/53, 1/40 DUTY, LCD CONTROLLER/DRIVER WITH BUILT-IN RAM

NEC => Renesas Technology 

µPD16680

3.2 Logic System Pins (1/2)

Pin Symbol

WS

Pin Name

Word length select pin

(Word Select)

DACHA

STB

D/A converter select pin

Strobe

E(SCK)

Enable(shift clock)

D0(DATA)

Data-bus(data)

D1 to D3

Data-bus

D4 to D6

Data-bus

D7(NS)

Data-bus(nibble select)

TESTOUT

/RESET

TEST signal output

Reset

Pin No.

92

78

93

94

84

85 to 87

88 to 90

91

97

95

I/O

Function Description

I This pin selects the word length.

At High level, it become an 8-bit parallel interface.

At Low level, when D7(NS) is High level, it become a serial

interface.

When the word length is 4 bits, data is transferred in the

upper-to-low sequence by mean of data busses D0 to D3.

The word length cannot be changed after power-on.

I This pin selects whether to use the internal D/A converter for

LCD driving voltage adjustment or not.

At High level, D/A converter is used. At Low level, unused.

I This pin is select signal of device, strobe signal for data

transfer. Data transfer is initialized at falling/rising edge of

STB.

Data can be input/output at Low level either in parallel

interface or serial interface mode.

When STB is High level, Enable/shift clock is bypassed.

I When using parallel interface mode, this pin becomes the

data enable input. In reading-in, data is fetched into the

interface buffer at rising edge. In reading-out, data is fetched

from interface buffer at falling edge.

When using serial interface mode, this pin becomes the data

shit clock.

In reading-in, data is fetched into the interface buffer at rising

edge.

In reading-out, data is fetched from interface buffer at falling

edge.

I/O When using parallel interface mode, this pin becomes the D0

bit of data-bus.

When using serial interface mode, this pin becomes the

input/output pin of the command and display data (3 states).

I/O When using parallel interface mode, these pin becomes the

D1 to D3 bits of data-bus. When using serial interface mode,

keep them H or L.

I/O When using parallel interface mode, these pin become the D4

to D6 bits of data-bus. When using serial interface mode, keep

them H or L.

I/O When word select (WS) is High level, this pin becomes the D7

bit of data-bus.

When word select (WS) is Low level, This pin becomes nibble

select pin. At High level, selected 4-bit parallel interface.

At Low level, selected serial interface.

O When to do test, this pin is output for test signal.

When using in normal operation, this pin leave open.

I At Low level, the µPD16680 is initialized.

Data Sheet S12694EJ2V0DS00

7

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