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UPD16434G-001-12 Ver la hoja de datos (PDF) - NEC => Renesas Technology

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UPD16434G-001-12
NEC
NEC => Renesas Technology NEC
UPD16434G-001-12 Datasheet PDF : 64 Pages
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µ PD16434
Table 2–2. LCD Dual Mode Row Driver Function Selection
M2, M1, M0Note 1
Number of time
divisions
R0/R8 to R7/R15 R15/C42 to R8/C49
000
8
001
R0 to R7
C42 to C49
010
011
100
16
R8 to R15Note 2
101
110
R0 to R7Note 3
111
R15 to R8
Notes 1. M2, M1, M0 is code specified by SMM command.
2. Some other chip handles R0 to R7 outputs.
3. Some other chip handles R8 to R15 outputs.
M2, M1, M0 = 111 is for single chip configuration. In this case, R15/C42 to
R8/C49 are used as row signal outputs, and all 16 row signals are output
from this chip.
These drivers perform switching of the analog level in correspondence to the contents of the display data read out
from the data memory and the timing signals supplied from the LCD timing control circuit, according to the select level,
non-select level, and phase supplied from the LCD voltage control circuit, and generates and outputs row and column
driver signals in order to directly drive the LCD.
20
Data Sheet S10299EJ4V0DS00

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