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UPC2533GS Ver la hoja de datos (PDF) - NEC => Renesas Technology

Número de pieza
componentes Descripción
Fabricante
UPC2533GS
NEC
NEC => Renesas Technology NEC
UPC2533GS Datasheet PDF : 36 Pages
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µPC2533
2.2 MIX1 Block
Fig. 2-2 MIX1 Block
T1
VT
+
To 10.7 MHz
BPF
VCC
From
LPF
23
31
32
17
29
27
Q101
Q102
Q104
Q103
R11
OSC1
Q105
Q109
1
Q108
Q106 Q107
R109
R110
R112
Buff1
Note
R111
R107
R108
28
33
To RF AGC circuit (Fig. 2-4)
30
Note Output impedance and input impedance of Buff1 are 330 and 15 k, respectively.
MIX1 (Q101 to Q108) is a DBM (double balanced mixer).
MIX1 output is supplied to 10.7 MHz ceramic filter via Buff1 (output impedance: 330 ) for impedance matching.
The local oscillation signal is applied to the bases of Q101 to Q104, and the RF signal to the base of Q105. MIX1
(Q101 to 108) multiplies the local oscillation signal by RF signal, and converts to the resonance frequency of IFT T1
for output.
The local oscillation signal is output from pin 1 via Q109 (OSC Buff). It has an amplitude of 110 dBµV and can
be directly input to CMOS LSI for use by the PLL synthesizer.
The RF signal applied to the base of Q105 is also input to the detector of the RF AGC circuit.
12

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