UDN2916EB-T Ver la hoja de datos (PDF) - Allegro MicroSystems
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UDN2916EB-T Datasheet PDF : 10 Pages
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2916
DUALFULL -BRIDGE
MOTOR DRIVER
APPLICATIONS INFORMATION
PWM CURRENT CONTROL
The UDN2916B/EB/LB dual bridges are designed to
drive both windings of a bipolar stepper motor. Output
current is sensed and controlled independently in each
bridge by an external sense resistor (R S ), internal com-
parator, and monostable multivibrator.
PWM OUTPUT CURRENT WAVE FORM
V PHAS E
When the bridge is turned ON, current increases in
the motor winding and it is sensed by the external sense
resistor until the sense voltage (VSENSE ) reaches the level
set at the comparator’s input:
I TRIP = VREF / 10 RS
The comparator then triggers the monostable which
turns OFF the source driver of the bridge. The actual
load current peak will be slightly higher than the trip point
(especially for low-inductance loads) because of the
internal logic and switching delays. This delay (t d ) is
typically 2 µs. After turn-o , the motor current decays,
circulating through the ground-clamp diode and sink
transistor. The source driver’s OFF time (and therefore
the magnitude of the current decrease) is determined by
the monostable’s external RC timing components, where
to = R T C T within the range of 20 k Ω to 100 k Ω and
100 pF to 1000 pF.
The xed-o time should be short enough to keep
the current chopping above the audible range (< 46 µs)
and long enough to properly regulate the current. Be-
cause only slow-decay current control is available, short
o times (< 10 µs) require additional e orts to ensure
proper current regulation. Factors that can negatively
a ect the ability to properly regulate the current when
using short o times include: higher motor-supply volt-
age, light load, and longer than necessary blank time.
When the source driver is re-enabled, the winding
current (the sense voltage) is again allowed to rise to the
comparator’s threshold. This cycle repeats itself, main-
taining the average motor winding current at the desired
level.
+
I OUT 0
–
ITR IP
td
to
Dwg. WM-003-1A
LOAD CURRENT PATHS
VB B
Loads with high distributed capaci-tances may
result in high turn-ON current peaks. This peak (appear-
ing across RS) will attempt to trip the comparator, result-
ing in erroneous current control or high-frequency
oscillations. An external R CC C time delay should be used
to further delay the action of the comparator. Depending
on load type, many applications will not require these
external components (SENSE connected to E).
BR IDGE ON
RS
SOUR CE OFF
ALL OFF
Dwg. E P -006-1
115 Northeast
Box 15036
5
Worcester, Massachusetts 01615-0036 (508) 853-5000
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