TSL2580 Ver la hoja de datos (PDF) - Unspecified
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TSL2580 Datasheet PDF : 32 Pages
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TSL2580, TSL2581
LIGHT-TO-DIGITAL CONVERTER
TAOS098 − MARCH 2010
Command Register
The command register specifies the address of the target register for subsequent read and write operations and
contains eight bits as described in Table 3. The command register defaults to 00h at power on.
Table 3. Command Register
Bit : 7
6
5
4
CMD
TRANSACTION
3
2
1
ADDRESS
0
Reset
00h
FIELD
CMD
TRANSACTION
ADDRESS
BIT
DESCRIPTION
7
Select command register. Must write as 1 when addressing COMMAND register.
Select type of transaction to follow in subsequent data transfers:
FIELD VALUE TRANSACTION
DESCRIPTION
00
Byte protocol SMB read/write byte protocol
6:5
01
Word protocol SMB read/write word protocol
10
Block protocol
SMB and I2C read/write block protocol. Regarding SMBus block
transfer, see note below.
11
Special function
Specifies a special command function in the ADDRESS field (see
below).
Register Address/Special Function. This field selects the specific control or status register for following
write and read commands according to Table 2. When the TRANSACTION field is set to 11b, this field
specifies a special command function as outlined below.
FIELD VALUE
SPECIAL
FUNCTION
DESCRIPTION
00000
Reserved
Reserved. Write as 0000b.
00001
Interrupt clear Clear any pending interrupt and is a write−once−to−clear bit
4:0
When the Timing Register is set to 00h, a SendByte command
00010
Stop manual
integration
with the ADDRESS field set to 0010b will stop a manual
integration. The actual length of the integration cycle may be read
in the MANUAL INTEGRATION TIMER Register.
00011
Start manual
integration
When the Timing Register is set to 00h, a SendByte command
with the ADDRESS field set to 0011b will start a manual
integration. The actual length of the integration cycle may be read
in the MANUAL INTEGRATION TIMER Register.
x11xx
Reserved
Reserved. Write as 11xxb.
NOTE: An I2C block transaction will continue until the Master sends a stop condition. See Figure 13 and Figure 14. Unlike the I2C protocol, the
SMBus read/write protocol requires a Byte Count. All four ADC Channel Registers (14h through 17h) can be read simultaneously in a
single SMBus transaction. This is the only 32-bit data block supported by the TSL258x SMBus protocol. The TRANSACTION Field Value
must be set to 10b, and a read condition should be initiated with a COMMAND CODE of D3h. By using a COMMAND CODE of D3h during
an SMBus Block Read Protocol, the TSL258x device will automatically insert the appropriate Byte Count (Byte Count = 4) as illustrated
in Figure 14. A write condition should not be used in conjunction with the 13h register.
NOTE: Only the Send Byte Protocol should be used when clearing interrupts.
Copyright E 2010, TAOS Inc.
12
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