TSC80251 Ver la hoja de datos (PDF) - Temic Semiconductors
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TSC80251 Datasheet PDF : 219 Pages
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TSC80251
Memory Address Space
16 Mbytes
FFFFh
C51 Architecture
Code Memory
FF:0000h 0000h
02:0000h
01:0000h
FFFFh
C51 Architecture
External Data Memory
0000h
00:0000h
FFh
C51 Architecture
Internal Data Memory
00h
SFR Space
512 Bytes
S:1FFh
S:100h
C51 Architecture FFh
80h
S:000h
SFRs
S:07Fh
Register File
64 Bytes
3Fh
08h
C51 Architecture R7
00h R0 Register File.
Figure 3.3. Mappings C51 Architecture to C251 Architecture Address Spaces
Figure 3.4. TSC80251 Memory Space
3.4. TSC80251 Register File
The TSC80251 register file consists of 40 byte locations: 0-31 and 56-63, as shown in Figure 3.5. These locations are
accessible as bits, bytes, words and dwords. Several locations are dedicated to special registers; the others are
general–purpose registers.
Register file locations 0-7 actually consist of four switchable banks of eight registers each, as illustrated in
Figure 3.6. The four banks are implemented as the first 32 bytes of on–chip RAM and are always accessible as locations
00:0000h-00:001Fh in the memory address space. Only one of the four banks is accessible via the register file at a given
time. The accessible, or “active”, bank is selected by bits RS1 and RS0 in the PSW register, as shown in Table 3.2. This
bank selection can be used for fast context switches.
Register file locations 8-31 and 56-63 are always accessible. These locations are implemented as registers in the CPU.
Register file locations 32-55 are reserved and cannot be accessed.
Bank
Bank 0
Bank 1
Bank 2
Bank 3
3.4
Table 3.2. Register Bank Selection
Address Range
PSW Selection Bits
RS1
RS0
00h-07h
0
0
08h-0Fh
0
1
10h-17h
1
0
18h-1Fh
1
1
Rev. C – May 7, 1999
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