TSC80251 Ver la hoja de datos (PDF) - Temic Semiconductors
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TSC80251 Datasheet PDF : 219 Pages
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TSC80251
Memory Type
Code
External Data
Internal Data
SFRs
Register
Size
64 Kbytes
64 Kbytes
128 bytes
128 bytes
128 bytes
8 bytes
Table 3.1. Address Mappings
C51 Architecture
Location
Data Addressing
0000h-FFFFh
Indirect using MOVC
0000h-FFFFh
Indirect using MOVX
00h-7Fh
Direct, Indirect
80h-FFh
Indirect
S:80h-S:FFh
Direct
R0-R7
Register
C251 Architecture
Location
FF:0000h-FF:FFFFh
01:0000h-01:FFFFh
00:0000h-00:007Fh
00:0080h-00:00FFh
S:0080h-S:0FFh
00:0000h–00:001Fh
The 64–Kbyte external data memory for 80C51 microcontrollers is mapped into the memory region specified by bits
16–23 of the data pointer DPX, i.e., DPXL, which is accessible as register file location 57 and also as SFR at S:084h.
The reset value of DPXL is 01h, which maps the external memory to region 01: as shown in Figure 3.3. You can change
this mapping by writing a different value to DPXL. A mapping of the C51 Architecture external data memory into any
64–Kbyte memory region in the C251 Architecture provides complete runtime compatibility because the lower 16
address bits are identical in both architectures.
The 256 bytes of on–chip data memory for 80C51 microcontrollers (00h–FFh) are mapped to addresses
00:0000h–00:00FFh to ensure complete runtime compatibility. In the C51 Architecture, the lower 128 bytes (00h–7Fh)
are directly and indirectly addressable; however the upper 128 bytes are accessible by indirect addressing only. In the
C251 Architecture, all locations in region 00: are accessible by direct, indirect, and displacement addressing.
The 128–byte SFR space for 80C51 microcontrollers is mapped into the 512–byte SFR space of the C251 Architecture
starting at address S:080h, as shown in Figure 3.3. This provides complete compatibility with direct addressing of
80C51 microcontroller SFRs (including bit addressing). The SFR addresses are unchanged in the new Architecture.
In the C251 Architecture, SFRs, A, B, DPL, DPH and SP, as well as the new DPXL and SPH, reside in the register file
for high performance. However, to maintain compatibility, they are also mapped into the SFR space at the same
addresses as in the C51 Architecture.
Rev. C – May 7, 1999
3.3
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