TSC80251 Ver la hoja de datos (PDF) - Temic Semiconductors
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TSC80251 Datasheet PDF : 219 Pages
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TSC80251
2.2.2. Clock and Reset Unit
The timing source for the TSC80251 microcontroller can be an external oscillator or an internal oscillator with an
external crystal/resonator. The basic unit of time in TSC80251 is the state time (or state), which is two oscillator
periods. The state time is divided into phase P1 and phase P2 (See Figure 2.3. ).
XTAL1
Phase 1
P1
Phase 2
P2
TOSC
2 TOSC = State Time
State 1
P1 P2
State 2
P1 P2
State 3
P1 P2
State 4
P1 P2
State 5
P1 P2
State 6
P1 P2
Figure 2.3. Clocking Definitions
The TSC80251 peripherals operate on a peripheral cycle, which is six state times (this peripheral cycle is not a
characteristic of the C251 Architecture). A one–clock interval in a peripheral cycle is denoted by its state and phase
(SxPy). For simplicity purpose, XTAL1 signal has been used in this figure. In fact this is the prescaler output that drives
the core. The clock prescaler being a software programmable device, the effective core clock can be dynamically
adapted to the application speed and power consumption needs.
The reset unit places the TSC80251 into a known state. A chip reset is initiated by asserting the RST pin or allowing
the Watchdog Timer to time out when the TSC80251 has one.
2.2.3. Interrupt Handler Unit
The Interrupt Handler Unit can receive interrupt requests from many sources: internal peripheral sources, external
sources and TRAP instruction. When the interrupt handler grants an interrupt request, the CPU discontinues the normal
flow of instructions and branches to a routine that services the source that requested the interrupt. You can enable or
disable the interrupts individually (except for TRAP and NMI which cannot be disabled) and you can chose among
one to four priority levels for each interrupt.
2.4
Rev. C – May 7, 1999
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