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8XL196NP Ver la hoja de datos (PDF) - Intel

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8XL196NP Datasheet PDF : 34 Pages
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8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Name
WRH#
WRL#
XTAL1
XTAL2
Table 6. Signal Descriptions (Continued)
Type
O
Description
Write High
During 16-bit bus cycles, this active-low output signal is asserted for high-byte
writes and word writes to external memory. During 8-bit bus cycles, WRH# is
asserted for all write operations.
WRH# shares a package pin with BHE#.
When this pin is configured as a special-function signal (P5_MODE.5 = 1), the
chip configuration register 0 (CCR0) determines whether it functions as BHE# or
WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.
O Write Low
During 16-bit bus cycles, this active-low output signal is asserted for low-byte writes
and word writes to external memory. During 8-bit bus cycles, WRL# is asserted for
all write operations.
WRL# shares a package pin with WR#.
When this pin is configured as a special-function signal (P5_MODE.2 = 1), the
chip configuration register 0 (CCR0) determines whether it functions as WR# or
WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
I Input Crystal/Resonator or External Clock Input
Input to the on-chip oscillator and the internal clock generators. The internal clock
generators provide the peripheral clocks, CPU clock, and CLKOUT signal. When
using an external clock source instead of the on-chip oscillator, connect the clock
input to XTAL1. The external clock signal must meet the VIH specification for XTAL1.
O Inverted Output for the Crystal/Resonator
Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design
uses an external clock source instead of the on-chip oscillator.
16

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