AD7716BS Ver la hoja de datos (PDF) - Analog Devices
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AD7716BS Datasheet PDF : 16 Pages
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AD7716
MASTER MODE TIMING CHARACTERISTICS1, 2 (AVDD = DVDD = +5 V ؎ 5%; AVSS = –5 V ؎ 5%; AGND = DGND = 0 V;
fCLKIN = 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted)
Parameter
Limit at TMIN, TMAX
(B Version)
Units
Conditions/Comments
fCLKIN3, 4
tr5
tf5
t7
t8
t9
t10
t11
t12
t13
t14
t15
t166
t177
t18
t19
t20
t21
400
8
40
40
1/fCLKIN
1/fCLKIN
1/2fCLKIN + 30
50
40
50
1/fCLKIN
40
1/fCLKIN
45
1/2fCLKIN + 50
1/2fCLKIN + 10
1/2fCLKIN + 60
50
20
1/2fCLKIN + 50
2/fCLKIN
kHz min
MHz max
ns max
ns max
ns min
ns min
ns max
ns max
ns max
ns min
ns
ns max
ns
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns
CLKIN Frequency
Digital Output Rise Time. Typically 20 ns
Digital Output Fall Time. Typically 20 ns
CASCIN Pulse Width
CASCIN to DRDY Setup Time
DRDY Low to SCLK Low Delay
CLKIN High to DRDY Low, SCLK Active, RFS Active
CLKIN High to SCLK High Delay
SCLK Width
SCLK Period
SCLK High to RFS High Delay
RFS Pulse Width
SCLK High to SDATA Valid Delay
SCLK Low to SDATA High Impedance Delay
CLKIN High to DRDY High Delay
CLKIN High to RFS High Impedance, SCLK High Impedance
SCLK Low to CASCOUT High Delay
CASCOUT Pulse Width
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 1 and 3.
3CLKIN duty cycle range is 40% to 60%.
4The AD7716 is production tested with fCLKIN at 8 MHz in the slave mode. It is guaranteed by characterization to operate at 400 kHz and 8 MHz in master mode.
5Specified using 10% and 90% points on waveform of interest.
6t16 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
7t17 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
CASCIN (I)
CLKIN (I)
DRDY (O)
SCLK (O)
RFS (O)
SDATA (O)
CASCOUT (O)
t7
t8
t9
t10
t 16
t 11
t 12
t 13
t18
t19
t 12
t 14
t15
t19
DB31
CH1
DB30 DB29 DB25 DB24 DB23 DB2
CH1
CH1 CH1
CH1
CH1
CH4
t17
DB1
DB0
CH4
CH4
t21
t20
Figure 3. Master Mode Timing Diagram
–4–
REV. A
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