IDT723614L20PQFI(2002) Ver la hoja de datos (PDF) - Integrated Device Technology

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IDT723614L20PQFI
(Rev.:2002)

CMOS SyncBiFIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2

Integrated Device Technology 

IDT723614 CMOS SYNCBIFIFO™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

CLKA

tCLKH

FFA HIGH

CSA

W/RA

MBA

ENA

A0 - A35

ODD/

EVEN

PEFA

NOTE:

1. Written to FIFO1.

tCLK

tCLKL

tENS

tENS

tENH

tENH

tENS

tENH

tENS

tENH

tDS

tDH

W1(1)

tPDPE

Valid

tENS

tENH

W2(1)

tPDPE

Valid

Figure 6. Port-A Write Cycle Timing for FIFO1

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

tENS

tENH

No Operation

3146 drw06

CLKB

FFB HIGH

CSB

W/RB

ENB

SW1,

SW0

BE

SIZ1,

SIZ0

B0-B35

tSZS

tSZS

(0,0)

tSZH

tSZH

t ENS

t ENS

t ENS

tSWS

tENH

tSWH

(0,0)

tDS

tDH

NOT (1,1) (1)

tENS

ODD/

EVEN

tPPE

PEFB

NOTE:

1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register

VALID

tPDPE

VALID

DATA SWAP TABLE FOR LONG-WORD WRITES TO FIFO2

SWAP MODE

SW1

SW0

L

L

L

H

H

L

B35-27

A

D

C

DATA WRITTEN TO FIFO2

B26-18

B17-B9

B

C

C

B

D

A

B8-B0

D

A

B

A35-27

A

A

A

DATA READ FROM FIFO2

A26-A18

A17-A9

B

C

B

C

B

C

H

H

B

A

D

C

A

B

C

Figure 7. Port-B Long-Word Write Cycle Timing for FIFO2

17

tENH

3146 drw 07

A8-A0

D

D

D

D

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